Maxim DS87C530 Clock User Manual

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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock

23 of 47

IDLE MODE

Setting the lsb of the Power Control register (PCON; 87h) invokes the Idle mode. Idle will leave internal

clocks, serial ports and timers running. Power consumption drops because the CPU is not active. Since

clocks are running, the Idle power consumption is a function of crystal frequency. It should be

approximately one-half the operational power at a given frequency. The CPU can exit the Idle state with

any interrupt or a reset. Idle is available for backward software compatibility. The system can now reduce

power consumption to below Idle levels by using PMM1 or PMM2 and running NOPs.

STOP MODE ENHANCEMENTS

Setting bit 1 of the Power Control register (PCON; 87h) invokes the Stop mode. Stop mode is the lowest

power state since it turns off all internal clocking. The I

of a standard Stop mode is approximately 1 mA

but is specified in the Electrical Specifications. The CPU will exit Stop mode from an external interrupt

or a reset condition. Internally generated interrupts (timer, serial port, watchdog) are not useful since they

require clocking activity. One exception is that a RTC interrupt can cause the device to exit Stop mode.

This provides a very power efficient way of performing infrequent yet periodic tasks.

The DS87C530/DS83C530 provide two enhancements to the Stop mode. As documented below, the

device provides a bandgap reference to determine Power-fail Interrupt and Reset thresholds. The default

state is that the bandgap reference is off while in Stop mode. This allows the extremely low-power state

mentioned above. A user can optionally choose to have the bandgap enabled during Stop mode. With the

bandgap reference enabled, PFI and Power-fail Reset are functional and are a valid means for leaving

Stop mode. This allows software to detect and compensate for a brownout or power supply sag, even

when in Stop mode.

In Stop mode with the bandgap enabled, I

will be approximately 50mA compared with 1mA with the

bandgap off. If a user does not require a Power-fail Reset or Interrupt while in Stop mode, the bandgap

can remain disabled. Only the most power sensitive applications should turn off the bandgap, as this

results in an uncontrolled power-down condition.

The control of the bandgap reference is located in the Extended Interrupt Flag register (EXIF; 91h).

Setting BGS (EXIF.0) to a 1 will keep the bandgap reference enabled during Stop mode. The default or

reset condition is with the bit at a logic 0. This results in the bandgap being off during Stop mode. Note

that this bit has no control of the reference during full power, PMM, or Idle modes.

The second feature allows an additional power saving option while also making Stop easier to use. This is

the ability to start instantly when exiting Stop mode. It is the internal ring oscillator that provides this

feature. This ring can be a clock source when exiting Stop mode in response to an interrupt. The benefit

of the ring oscillator is as follows.

Using Stop mode turns off the crystal oscillator and all internal clocks to save power. This requires that

the oscillator be restarted when exiting Stop mode. Actual startup time is crystal-dependent, but is

normally at least 4ms. A common recommendation is 10ms. In an application that will wake up, perform

a short operation, then return to sleep, the crystal startup can be longer than the real transaction. However,

the ring oscillator will start instantly. Running from the ring, the user can perform a simple operation and

return to sleep before the crystal has even started. If a user selects the ring to provide the startup clock and

the processor remains running, hardware will automatically switch to the crystal once a power-on reset

interval (65,536 clocks) has expired. Hardware uses this value to assure proper crystal start even though

power is not being cycled.

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Maxim DS87C530 Clock User Manual