Maxim DS87C530 Clock User Manual


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DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock
26 of 47
read the PFI flag at WDCON.4. A PFI condition sets this bit to a 1. The flag is independent of the
interrupt enable and software must manually clear it. If the PFI is enabled and the bandgap select bit
(BGS) is set, a PFI will bring the device out of Stop mode.
WATCHDOG TIMER
To prevent software from losing control, the DS87C530/DS83C530 include a programmable watchdog
timer. The Watchdog is a free-running timer that sets a flag if allowed to reach a preselected timeout. It
can be (re)started by software.
A typical application is to select the flag as a reset source. When the Watchdog times out it sets its flag,
which generates reset. Software must restart the timer before it reaches its timeout or the processor is
reset.
Software can select one of four timeout values. Then, it restarts the timer and enables the reset function.
After enabling the reset function, software must then restart the timer before its expiration or hardware
will reset the CPU. Both the Watchdog Reset Enable and the Watchdog Restart control bits are protected
by a “Timed Access” circuit. This prevents errant software from accidentally clearing the Watchdog.
Timeout values are precise since they are a function of the crystal frequency as shown in Table 7. For
reference, the time periods at 33MHz also are shown.
The Watchdog also provides a useful option for systems that do not require a reset circuit. It will set an
interrupt flag 512 clocks before setting the reset flag. Software can optionally enable this interrupt source.
The interrupt is independent of the reset. A common use of the interrupt is during debug, to show
developers where the Watchdog times out. This indicates where the Watchdog must be restarted by
software. The interrupt also can serve as a convenient time-base generator or can wake-up the processor
from power saving modes.
The Watchdog function is controlled by the Clock Control (CKCON–8Eh), Watchdog Control
(WDCON–D8h), and Extended Interrupt Enable (EIE–E8h) SFRs. CKCON.7 and CKCON.6 are WD1
and WD0, respectively, and they select the Watchdog timeout period as shown in Table 7.
Table 7. Watchdog Timeout Values
WD1 WD0
INTERRUPT
TIMEOUT
TIME (33MHz) RESET TIMEOUT TIME (33MHz)
0 0 2
17
clocks 3.9718ms 2
17
+ 512 clocks 3.9874ms
0 1 2
20
clocks 31.77ms 2
20
+ 512 clocks 31.79ms
1 0 2
23
clocks 254.20ms 2
23
+ 512 clocks 254.21ms
1 1 2
26
clocks 2033.60ms 2
26
+ 512 clocks 2033.62ms
As shown above, the Watchdog Timer uses the crystal frequency as a time base. A user selects one of
four counter values to determine the timeout. These clock counter lengths are 2
17
= 131,072 clocks; 2
20
=
1,048,576; 2
23
= 8,388,608 clocks; and 2
26
= 67,108,864 clocks. The times shown in Table 7 are with a
33MHz crystal frequency. Once the counter chain has completed a full interrupt count, hardware will set
an interrupt flag. Regardless of whether the user enables this interrupt, there are then 512 clocks left until
the reset flag is set. Software can enable the interrupt and reset individually. Note that the Watchdog is a
free-running timer and does not require an enable.
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