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Summary of Operation Timings
Operation Timing Specifications
Parameter Description Typical Relevant Note(s)
Tprw_up Power Applied to Processor Ready Delay (USB) 6 seconds Notes 4 and 5
Tprw_up_ttl Trigger or Wake Low to Processor Ready Delay (TTL) 5 seconds Note 4
Tdec_idle Trigger Low to Decode complete Delay 90 msec Notes 1 and 2
Tdec_sleep Trigger Low to Decode complete Delay 120 msec Notes 1 and 3
Trig_min Minimum Duration of Trigger Signal 20 msec
Trig_wake_min_pu
Minimum Activation Time for Trigger or
Wake Signal to Power Up TTL Unit
2 seconds
Notes:
1. Timing is the same for Both TTL or USB version
2. Processor is in Idle Mode when nTrig signal is received
3. Processor is in Sleep Mode when nTrig signal is received
4. Typical time specified may vary depending on the enumeration time of the USB host.
5. Typical times specified are valid for an IS4920 or an IS4921 with a firmware version of 15848 or
higher. Units with a firmware version lower than 15848 may require up to 3 seconds of an additional
time.