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© National Instruments Corporation 61 NI cDAQ-9172 User Guide and Specifications
on each rising edge of a filter clock. The NI cDAQ-9172 chassis uses an
onboard oscillator to generate the filter clock with a 40 MHz frequency.
For more information, refer to the NI-DAQmx Help. The NI-DAQmx Help
is available after installation from Start»Programs»National
Instruments»NI-DAQ»NI-DAQmx Help.
Note NI-DAQmx only supports filters on counter inputs.
The following is an example of low to high transitions of the input signal.
High to low transitions work similarly.
Assume that an input terminal has been low for a long time. The input
terminal then changes from low to high, but glitches several times. When
the filter clock samples the signal high on N consecutive edges, the low to
high transition is propagated to the rest of the circuit. The value of N
depends on the filter setting, as listed in Table 7.
You can configure the filter setting for each input independently. On power
up, the filters are disabled. Figure 41 shows an example of a low to high
transition on an input with its filter set to 125 ns (N = 5).
Figure 41. Filter Example
Enabling filters introduces jitter on the input signal. For the 125 ns and
6.425 µs filter settings, the jitter is up to 25 ns. On the 2.56 ms setting, the
jitter is up to 10.025 µs.
Table 7. Counter Input Filters
Filter Setting
N (Filter Clocks
Needed to
Pass Signal)
Pulse Width
Guaranteed to
Pass Filter
Pulse Width
Guaranteed to
Not Pass Filter
125 ns 5 125 ns 100 ns
6.425 µs 257 6.425 µs 6.400 µs
2.56 ms ~101,800 2.56 ms 2.54 ms
Disabled — — —
1 2 3 1 4 1 2 3 4 5
PFI Terminal
Filter Clock
(40 MHz)
Filtered Input
Filtered input goes high
when terminal is sampled
high on five consecutive
filter clocks.