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PCI-4451/4452 User Manual viii
©
National Instruments Corporation
Figures
Figure 3-1. Digital Function Block Diagram........................................................... 3-1
Figure 3-2. Analog Function Block Diagram.......................................................... 3-2
Figure 3-3. Below-Low-Level Triggering Mode.....................................................3-7
Figure 3-4. Above-High-Level Triggering Mode.................................................... 3-8
Figure 3-5. Inside-Region Triggering Mode ...........................................................3-8
Figure 3-6. High-Hysteresis Triggering Mode........................................................ 3-8
Figure 3-7. Low-Hysteresis Triggering Mode.........................................................3-9
Figure 3-8. RTSI Bus Signal Connection................................................................ 3-10
Figure 4-1. Analog Pin Connections .......................................................................4-2
Figure 4-2. Digital Pin Connections........................................................................4-5
Figure 4-3. Analog Input Stage ............................................................................... 4-9
Figure 4-4. Analog Output Channel Block Diagram............................................... 4-11
Figure 4-5. Digital I/O Connections........................................................................4-13
Figure 4-6. Typical Posttriggered Acquisition ........................................................ 4-15
Figure 4-7. Typical Pretriggered AcquisitionPFI1 .................................................. 4-16
Figure 4-8. EXTSTROBE* Signal Timing .............................................................4-18
Figure 4-9. GPCTR0_SOURCE Signal Timing...................................................... 4-19
Figure 4-10. GPCTR0_OUT Signal Timing .............................................................4-20
Figure 4-11. GPCTR1_SOURCE Signal Timing...................................................... 4-21
Figure 4-12. GPCTR1_OUT Signal Timing .............................................................4-22
Figure 4-13. GPCTR Timing Summary .................................................................... 4-23
Figure 6-1. Input Frequency Response.................................................................... 6-5
Figure 6-2. Input Frequency Response Near the Cutoff..........................................6-6
Figure 6-3. Alias Rejection at the Oversample Rate ...............................................6-7
Figure 6-4. Comparison of a Clipped Signal to a Proper Signal ............................. 6-8
Figure 6-5. Signal Spectra in the DAC.................................................................... 6-11
Figure A-1. Idle Channel Noise (Typical)................................................................ A-4
Figure B-1. 68-Pin Digital Connector for any Digital Accessory............................ B-2
Tables
Table 3-1. Actual Range and Measurement Precision ........................................... 3-4
Table 3-2. Actual Range and Measurement Precision ........................................... 3-6
Table 4-1. Analog I/O Connector Pin Assignment ................................................4-3
Table 4-2. Analog I/O Signal Summary.................................................................4-4
Table 4-3. Digital I/O Connector Pin Assignment................................................. 4-6
Table 4-4. Digital I/O Signal Summary .................................................................4-8
User.book Page viii Tuesday, April 14, 1998 10:20 AM