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DS90C3202
3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver
General Description
The DS90C3202 is a 3.3V single/dual FPD-Link 10-bit color
receiver is designed to be used in Liquid Crystal Display
TVs, LCD Monitors, Digital TVs, and Plasma Display Panel
TVs. The DS90C3202 is designed to interface between the
digital video processor and the display device using the
low-power, low-EMI LVDS (Low Voltage Differential Signal-
ing) interface. The DS90C3202 converts up to ten LVDS
data streams back into 70 bits of parallel LVCMOS/LVTTL
data. The receiver can be programmed with rising edge or
falling edge clock. Optional wo-wire serial programming al-
lows fine tuning in development and production environ-
ments. With an input clock at 135 MHz, the maximum trans-
mission rate of each LVDS line is 945 Mbps, for an
aggregate throughput rate of 9.45 Gbps (945 Mbytes/s). This
allows the dual 10-bit LVDS Receiver to support resolutions
up to HDTV.
Features
n Up to 9.45 Gbit/s data throughput
n 8 MHz to 135 MHz input clock support
n Supports up to QXGA panel resolutions
n Supports HDTV panel resolutions and frame rates up to
1920 x 1080p
n LVDS 30-bit, 24-bit or 18-bit color data inputs
n Supports single pixel and dual pixel interfaces
n Supports spread spectrum clocking
n Two-wire serial communication interface
n Programmable clock edge and control strobe select
n Power down mode
n +3.3V supply voltage
n 128-pin TQFP Package
n Compliant to TIA/EIA-644-A-2001 LVDS Standard
Block Diagram
20147101
FIGURE 1. Receiver Block Diagram
September 2006
DS90C3202 3.3V 8 MHz to 135 MHz Dual FPD-Link Receiver
© 2006 National Semiconductor Corporation DS201471 www.national.com