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CHAPTER 18 SERIAL INTERFACE CHANNEL 0 (
µ
PD78078Y Subseries)
(3) Other signals
Figure 18-12 shows RELT and CMDT operations.
Figure 18-12. RELT and CMDT Operations
(4) Transfer start
Serial transfer is started by setting transfer data to the serial I/O shift register 0 (SIO0) when the following
two conditions are satisfied.
• Serial interface channel 0 operation control bit (CSIE0) = 1
• Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.
Cautions 1. If CSIE0 is set to “1” after data write to SIO0, transfer does not start.
2. Because the N-ch open-drain output must be set to high-impedance state for data
reception, write FFH to SIO0 in advance.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
(5) Error detection
In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination
device, that is, the serial I/O shift register 0 (SIO0). Thus, transmit error can be detected in the following
way.
(a) Method of comparing SIO0 data before transmission to that after transmission
In this case, if two data differ from each other, a transmit error is judged to have occurred.
(b) Method of using the slave address register (SVA)
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, COI
bit (match signal coming from the address comparator) of the serial operating mode register 0 (CSIM0)
is tested. If “1”, normal transmission is judged to have been carried out. If “0”, a transmit error is judged
to have occurred.
RELT
CMDT
SO0 Latch