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CHAPTER 18 SERIAL INTERFACE CHANNEL 0 (
µ
PD78078Y Subseries)
Figure 18-23. Example of Communication from Slave to Master (with 9-Clock Wait Selected for Both
Master and Slave) (2/3)
(b) Data
L
L
L
L
H
H
L
1
D1 D0D2D3D4D5D6D7
ACK
2345678
D6D7 D5 D4 D3
21345
9
L
L
L
SIO0 <- FFH SIO0 <- FFH
H
L
L
L
L
L
L
L
L
L
L
H
H
SIO0 write
COI
ACKD
CMDD
RELD
CLD
P27
SCL
SDA0
WUP
BSYE
ACKE
CMDT
RELT
CLC
WREL
SIC
INTCSI0
SIO0 write
COI
ACKD
CMDD
RELD
CLD
P27
WUP
BSYE
ACKE
CMDT
RELT
CLC
WREL
SIC
INTCSI0
CSIE0
P25
PM25
PM27
SIO0 <- dataSIO0 <- data
Processing in master device
Transfer line
Processing in slave device