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¡ SemiconductorMSM80C154S/83C154S
Timing Diagram
Basic timing
ACC & RAM
S1 S2 S3 S4 S5 S6
M1
S1 S2 S3 S4 S5 S6
M1
S1 S2 S3 S4 S5 S6
M2
S1 S2 S3 S4 S5 S6
M1
PCL PCL PCL PCL
PCH PCH PCH PCHPCHDPH & PORT DATAPCH
PC+1
TM+1
PC+1
TM+1
TM+1TM+1
PC+1PC+1PC+1
CYCLE
STEP
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
XTAL 1
ALE
RD/WR
PORT-0
PORT-2
CPU¨PORT
PORT¨CPU
PCH
PCL
DPL&Rr
DATA STABLE
PORT OLD DATA
DATA STABLE
PSEN
PCL
PORT NEW DATA
Port output/input
instruction execution
Instruction execution
External data memory instruction
execution
Instruction execution
Port output/input
instruction execution
Instruction execution
Instruction decoding Instruction decodingInstruction decoding