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Philips Semiconductors Product data
CBT338410-bit bus switch with 5-bit output enables
2001 Dec 20
4
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS
T
amb
= –40 to +85 °C
UNIT
Min Typ
1
Max
V
IK
Input clamp voltage V
CC
= 4.5 V; I
I
= –18 mA — — –1.2 V
I
I
Input leakage current V
CC
= 5.5 V; V
I
= GND or 5.5 V — — ±1 µA
I
CC
Quiescent supply current
2
V
CC
= 5.5 V; I
O
= 0, V
I
= V
CC
or GND — — 3 µA
∆I
CC
Additional supply current per input pin
2
V
CC
= 5.5 V, one input at 3.4 V, other inputs at V
CC
or GND
— — 2.5 mA
C
I
Control pins V
I
= 3.0 V or 0 — 4 — pF
C
I(OFF)
Port off capacitance V
O
= 3.0 V or 0, OE = V
CC
— 10 — pF
3
V
CC
= 4.5 V; V
I
= 0 V; I
I
= 64 mA — 5 7
r
on
3
On-resistance
V
CC
= 4.5 V; V
I
= 0 V; I
I
= 30 mA — 5 7
Ω
V
CC
= 4.5 V; V
I
= 2.4 V; I
I
= –15 mA — 10 15
V
P
Pass voltage V
I
= V
CC
= 5.0 V; I
O
= –100 µA 3.4 3.6 3.9 V
I
UCP
Undershoot static current protection V
CC
= 5.0 V, I
B
= 400 µA; OE = 5.0 V; V
B
≥ 3.0 V — 8 — mA
NOTES:
1. All typical values are at V
CC
= 5 V, T
amb
= 25 °C
2. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
3. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is
determined by the lowest voltage of the two (A or B) terminals.
AC CHARACTERISTICS
GND = 0 V; t
R;
C
L
= 50 pF
FROM
TO
LIMITS
SYMBOL PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC
= +5.0 V ±0.5 V
UNIT
(INPUT)
(OUTPUT)
Min Max
t
pd
Propagation delay
1
A or B B or A — .25 ns
t
en
Output enable time
to High and Low level
OE A or B 1.0 5.7 ns
t
dis
Output disable time
from High and Low level
OE A or B 1.0 5.2 ns
NOTE:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on–state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
LIMITS
SYMBOL PARAMETER DESCRIPTION
T
amb
=
–40 to +85 °C
V
CC
= 5 V, ±0.5 V
UNIT
MIN. MEAN MAX.
t
pd
Propagation delay (see Note 1) — — 250 ps
t
PZH
Output enable time to High level 1.6 3.4 5.6 ns
t
PHZ
Output enable time from High level 1.7 3.3 5.5 ns
t
PZL
Output enable time to Low level 2.3 4 6 ns
t
PLZ
Output enable time from Low level 2.5 4.5 6.6 ns
NOTE:
1. This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance); at +25 °C.