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Programmable Microelectronics Corp. Issue Date: February, 2004, Rev: 1.4
PMC Pm25LV512/010
sserddAkcolBkcolB215VL52mPkcolB010VL52mP
FFF700ot0000001kcolB1kcolB
FFFF00ot0008002kcolB2kcolB
FFF710ot000010A/N3kcolB
FFFF10ot000810A/N4kcolB
Table 8. Block Addresses
SECTOR_ERASE, BLOCK_ERASE: Before a byte can be reprogrammed, the sector/block which contains the
byte must be erased. In order to erase the Pm25LV512/010, two separate instructions must be executed. First, the
device must be write enabled via the WREN instruction. Then the SECTOR ERASE or BLOCK ERASE instruction
can be executed.
The BLOCK ERASE instruction erases every byte in the selected block if the block is not locked out. Block
address is automatically determined if any address within the block is selected. The BLOCK ERASE instruction
is internally controlled; it will automatically be timed to completion. During this time, all commands will be ignored,
except RDSR instruction. The Pm25LV512/010 will automatically return to the write disable state at the completion
of the BLOCK ERASE cycle.
CHIP_ERASE: As an alternative to the SECTOR and BLOCK ERASE, the CHIP ERASE instruction will erase
every byte in all blocks that are not locked out. First, the device must be write enabled via the WREN instruction.
Then the CHIP ERASE instruction can be executed. The CHIP ERASE instruction is internally controlled; it will
automatically be timed to completion. The CHIP ERASE cycle time maximum is 100 miliseconds. During the
internal erase cycle, all instructions will be ignored except RDSR. The Pm25LV512/010 will automatically return to
the write disable state at the completion of the CHIP ERASE.
HOLD: The HOLD# pin is used in conjunction with the CE# pin to select the Pm25LV512/010. When the device is
selected and a serial sequence is underway, HOLD# pin can be used to pause the serial communication with the
master device without resetting the serial sequence. To pause, the HOLD# pin must be brought low while the SCK
pin is low. To resume serial communication, the HOLD# pin is brought high while the SCK pin is low (SCK may still
toggle during HOLD). Inputs to the Sl pin will be ignored while the SO pin is in the high impedance state.
HARDWARE WRITE PROTECT: The Pm25LV512/010 has a write lockout feature that can be activated by assert-
ing the write protect pin (WP#). When the lockout feature is activated, locked-out sectors will be READ only. The
write protect pin will allow normal read/write operations when held high. When the WP# is brought low and WPEN
bit is "1", all write operations to the status register are inhibited. WP# going low while CE# is still low will interrupt
a write to the status register. If the internal status register write cycle has already been initiated, WP# going low will
have no effect on any write operation to the status register. The WP# pin function is blocked when the WPEN bit in
the status register is "0". This will allow the user to install the Pm25LV512/010 in a system with the WP# pin tied
to ground and still be able to write to the status register. All WP# pin functions are enabled when the WPEN bit is
set to "1".