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LINE STATUS REGISTER
This register is located at I/O address [base+5]. It is used to
provide various types of status information concerning the data transfer.
As Figure 22 shows, the Line Status Register indicates several types of
errors, an empty transmit buffer, a ready receive buffer, or a break on the
receive line.
DR --- Data ready:
Indicates data is present in the receive buffer or FIFO (16550). DR is reset by
reading the receive buffer register or receiver FIFO.
0
OE --- Overrun error:
Indicates the receive buffer was not read before the next character was received
and the character is destroyed. In 16550 FIFO mode, indicates the receive FIFO
is full and another character has been shifted in. The character in the shift
register is destroyed but is not transferred to the FIFO.
1
PE --- Parity error:
Indicates that the received data does not have the correct parity.
2
FE --- Framing error:
Indicates the received character had an invalid stop bit. The stop bit following
the last data or parity bit was a 0 bit (spacing level).
3
BI --- Break interrupt:
Indicates the receive data input has been in the spacing state (logic 0) for longer
than one full word transmission time. In 16550 FIFO mode, only one zero
character is loaded into the FIFO and transfers are disabled until the serial data
input goes to the mark state (logic 1) and a valid start bit is received.
4
THRE --- Transmitter holding register empty:
Indicates the transmitter holding register or FIFO (16550) is empty and it is
ready to accept new data. THRE is reset by writing data to the transmitter
holding register.
5
TEMT --- Transmitter empty:
Indicates the transmitter holding register or FIFO (16550) AND the transmitter
shift register are empty and are ready to receive new data. TEMT is reset by
writing a character to the transmitter holding register.
6
FFRX --- Error in RCVR FIFO (16550 FIFO mode only):
Always logic 0 in 16450 or 16550 non-FIFO mode.
Indicates one or more parity errors, framing errors, or break indications in the
receiver FIFO. FFRX is reset by reading the line status register.
7
DESCRIPTION
BIT
Figure 22 --- Line Status Register bit definitions
Bits BI, FE, PE, and OE are the sources of receiver line status
interrupts. The bits are reset by reading the line status register. In 16550
FIFO mode, these bits are associated with a specific character in the FIFO
and the exception is revealed only when that character reaches the top of
the FIFO.
Quatech
DS-102 User's Manual
21