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9.2. Application Headers
Table 9-5 to Table 9-9 below show the standard application header connections.
JA1
Pin Generic Header Name CPU board
Signal Name
Device
Pin
Pin Generic Header Name CPU board
Signal Name
Device
Pin
1 5V CON_5V - 2 0V GROUND 8
3 3V3 CON_3V3 - 4 0V GROUND -
5 AVCC CON_AVCC 121 6 AVss AVSS 123
7 AVref CON_VREF 125 8 ADTRG ADTRGn 66
9 AD0 AN0 118 10 AD1 AN1 119
11 AD2 AN2 120 12 AD3 AN3 122
13 DAC0 DA0 127 14 DAC1 DA1 128
15 IO_0 IO_0 52 16 IO_1 IO_1 53
17 IO_2 IO_2 54 18 IO_3 IO_3 55
19 IO_4 IO_4 56 20 IO_5 IO_5 57
21 IO_6 IO_6 58 22 IO_7 IO_7 59
23 IRQ3 NC - 24 IIC_EX NC -
25 IIC_SDA SDA1 65 26 IIC_SCL SCL1 64
Table 9-5: JA1 Standard Generic Header
JA2
Pin Generic Header Name CPU board
Signal Name
Device
Pin
Pin Header Name CPU board
Signal Name
Device
Pin
1 RESn RESn 91 2 EXTAL CON_EXTAL 98
3 NMI NMI 116 4 VSS1 GROUND
5 WDT_OVF WDTOVFn 104 6 SCIaTX TXD2 69
7 IRQ0 IRQ4n 124 8 SCIaRX RXD2 68
9 IRQ1 IRQ5n 126 10 SCIaCK SCK2 67
11 UD UD 60 12 CTS/RTS NC -
13 Up Up 106 14 Un Un 101
15 Vp Vp 94 16 Vn Vn 93
17 Wp Wp 92 18 Wn Wn 90
19 TMR0 TMR0 58 20 TMR1 TMR1 56
21 TRIGa TRIGa 57 22 TRIGb TRIGb 59
23 IRQ2 IRQ3n_ADTRGn 66 24 TRISTn TRISTn 17
25 - - 26 - - -
Table 9-6: JA2 Standard Generic Header
25