Filter
Top Products
INSTRUCTION SET S3C8275X/F8275X/C8278X/F8278X/C8274X/F8274X
6-80
SRP/SRP0/SRP1 — Set Register Pointer
SRP src
SRP0 src
SRP1 src
Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) ← src (3–7)
If src (1) = 0 and src (0) = 1 then: RP1 (3–7) ← src (3–7)
If src (1) = 0 and src (0) = 0 then: RP0 (4–7) ← src (4–7),
RP0 (3) ← 0
RP1 (4–7) ← src (4–7),
RP1 (3) ← 1
The source data bits one and zero (LSB) determine whether to write one or both of the register
pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register
pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.
Flags: No flags are affected.
Format:
Bytes Cycles Opcode
(Hex)
Addr Mode
src
opc src 2 4 31 IM
Examples: The statement
SRP #40H
sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location
0D7H to 48H.
The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to
68H.