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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor
Wishbone Communications
The following sections detail the standard handshaking that takes place when the processor communicates to a slave peripheral
or memory device connected to the relevant Wishbone interface port. Both of the ARM720T_LH79520's Wishbone ports can be
configured for 8-, 16- or 32-bit data transfer, depending on the width of the data bus supported by the connected slave device.
Configuration is achieved using the relevant IO_SEL_O or ME_SEL_O output, which defines where on the corresponding
DAT_O and DAT_I lines the data appears when writing and reading respectively.
Writing to a Slave Wishbone Peripheral Device
Data is written from the host processor (Wishbone Master) to a Wishbone-compliant peripheral device (Wishbone Slave) in
accordance with the standard Wishbone data transfer handshaking protocol. This data transfer cycle can be summarized as
follows:
• The host presents an address on its IO_ADR_O output for the register it wants to write to and valid data on its IO_DAT_O
output. It then asserts its IO_WE_O output to specify a Write cycle
• The host defines where the data will be sent on the IO_DAT_O line using its IO_SEL_O signal
• The slave device receives the address at its ADR_I input and prepares to receive the data
• The host asserts its IO_STB_O and IO_CYC_O outputs, indicating that the transfer is to begin. The slave device, monitoring
its STB_I and CYC_I inputs, reacts to this assertion by latching the data appearing at its DAT_I input into the requested
register and asserting its ACK_O signal – to indicate to the host that the data has been received
• The host, monitoring its IO_ACK_I input, responds by negating the IO_STB_O and IO_CYC_O signals. At the same time,
the slave device negates the ACK_O signal and the data transfer cycle is naturally terminated.
Reading from a Slave Wishbone Peripheral Device
Data is read by the host processor (Wishbone Master) from a Wishbone-compliant peripheral device (Wishbone Slave) in
accordance with the standard Wishbone data transfer handshaking protocol. This data transfer cycle can be summarized as
follows:
• The host presents an address on its IO_ADR_O output for the register it wishes to read. It then negates its IO_WE_O output
to specify a Read cycle
• The host defines where it expects the data to appear on its IO_DAT_I line using its IO_SEL_O signal
• The slave device receives the address at its ADR_I input and prepares to transmit the data from the selected register
• The host asserts its IO_STB_O and IO_CYC_O outputs, indicating that the transfer is to begin. The slave device, monitoring
its STB_I and CYC_I inputs, reacts to this assertion by presenting the valid data from the requested register at its DAT_O
output and asserting its ACK_O signal – to indicate to the host that valid data is present
• The host, monitoring its IO_ACK_I input, responds by latching the data appearing at its IO_DAT_I input and negating the
IO_STB_O and IO_CYC_O signals. At the same time, the slave device negates the ACK_O signal and the data transfer
cycle is naturally terminated.
Writing to a Slave Wishbone Memory Device
Data is written from the host processor (Wishbone Master) to a Wishbone-compliant memory device or memory controller
(Wishbone Slave) in accordance with the standard Wishbone data transfer handshaking protocol. This data transfer cycle can
be summarized as follows:
• The host presents an address on its ME_ADR_O output for the address in memory that it wants to write to and valid data on
its ME_DAT_O output. It then asserts its ME_WE_O output to specify a Write cycle
• The host defines where the data will be sent on the ME_DAT_O line using its ME_SEL_O signal
• The slave device receives the address at its ADR_I input and prepares to receive the data
• The host asserts its ME_STB_O and ME_CYC_O outputs, indicating that the transfer is to begin. The slave device,
monitoring its STB_I and CYC_I inputs, reacts to this assertion by storing the data appearing at its DAT_I input at the
requested address and asserting its ACK_O signal – to indicate to the host that the data has been received
• The host, monitoring its ME_ACK_I input, responds by negating the ME_STB_O and ME_CYC_O signals. At the same time,
the slave device negates the ACK_O signal and the data transfer cycle is naturally terminated.
18 CR0162 (v2.0) March 10, 2008