Filter
Top Products
Hi-Speed USB Transceiver with 1.8V ULPI Interface - Multi-Frequency Reference Clock
SMSC USB3310 REV C 5 Revision 1.11 (10-31-08)
PRODUCT PREVIEW
4
D2
VDD3.3
Power N/A 3.3V Regulator Output. A 2.2uF (<1 ohm
ESR) bypass capacitor to ground is
required for regulator stability. The
bypass capacitor should be placed as
close as possible to the USB3310.
5
D1
DM
I/O,
Analog
N/A D- pin of the USB cable.
6
E1
DP
I/O,
Analog
N/A D+ pin of the USB cable.
7
E2
DATA[7]
I/O,
CMOS
N/A
ULPI bi-directional data bus. DATA[7] is
the MSB.
8
E3
DATA[6]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
9
D3
DATA[5
I/O,
CMOS
N/A
ULPI bi-directional data bus.
10
E4
DATA[4]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
11
E5
CLKOUT
Output,
CMOS
N/A 60MHz reference clock output. All ULPI
signals are driven synchronous to the
rising edge of this clock.
12
D5
DATA[3]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
13
D4
DATA[2]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
14
C4
REFSEL[1]
Input,
CMOS
N/A These signals select one of the available
reference frequencies:
[1] [0] Description
0 0 13MHz
0 1 19.2MHz
1 0 26MHz
1 1 24MHz
15
B4
REFSEL[0]
Input,
CMOS
N/A
16
C5
DATA[1]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
17
B5
DATA[0]
I/O,
CMOS
N/A
ULPI bi-directional data bus. DATA[0] is
the LSB.
18
A5
NXT
Output,
CMOS
High The PHY asserts NXT to throttle the data.
When the Link is sending data to the
PHY, NXT indicates when the current
byte has been accepted by the PHY. The
Link places the next byte on the data bus
in the following clock cycle.
Table 1 USB3310 Pin Description (continued)
PIN
BALL NAME
DIRECTION/
TYPE
ACTIVE
LEVEL DESCRIPTION