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2.5OHCIInterrupts
2.6USBHostControllerAccesstoSystemMemory
2.7PhysicalAddressing
Processor
physical
address
Processor
virtual
address
Processor
MMU
00000000h
FFFFFFFFh
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Architecture
TheUSB1hostcontrollercanbecontrolledeitherbytheARMortheDSP.Ithastheabilitytointerrupt
eitherprocessor.
TheUSB1moduleneedstoaccesssystemmemorytoreadandwritetheOHCIdatastructuresanddata
buffersassociatedwithUSBtraffic.TheswitchfabricallowstheUSBhostcontrollertoaccesssystem
memory,asshownin.
Transactionsontheinternalbususephysicaladdresses,soallsystemmemoryaccessesinitiatedbythe
USBhostcontrollermustusephysicaladdresses.TheARMCPUcanbeconfiguredtousevirtual
addressing.Inthiscase,ARMsidesoftwaremanipulatesvirtualaddressesthatmayormaynotbe
identicaltophysicaladdresses.Whenvirtualaddressingisused,systemsoftwaremustperformthe
appropriatevirtualaddresstophysicaladdressandphysicaladdresstovirtualaddressconversionswhen
manipulatingtheUSBhostcontrollersdatastructuresandpointerstothosedatastructures.
Figure1showstheARMvirtualaddresstophysicaladdressconversion.
Figure1.RelationshipsBetweenVirtualAddressPhysicalAddress
SPRUFM8–September2008UniversalSerialBusOHCIHostController11
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