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Set the level of ECC protection. If User is selected, individual ECC options may be
changed. Other options besides Disabled serve as presets. For super mode, all of
memory is scrubbed every 8 hours.
Options: Disabled / Basic / Good / Super / Max User
ECC Error Checking
Enable the DRAM controller to read/write ECC check-bits on the DIMMs and it
allows the north bridge to check and correct ECC errors on the DRAM bus during
normal CPU or bus master read requests.
Options: Disabled / Enabled
ECC Error Log
Enable the MCA to log or report ECC errors on the DRAM bus.
NOTE: The MCA must still be programmed according to the desired MCE outcome.
Options: Disabled / Enabled
ChipKill
Enable 4-bit ECC mode (Chipkill) on dram controllers with all x4 ECC capable
DIMMs.
Options: Disabled / Enabled
ECC Scrub Redirection
Enable the northbridge to force a write to DRAM with corrected data when a
correctable error on the DRAM bus is detected during a normal CPU or bus master
read request.
Options: Disabled / Enabled
DRAM ECC Scrub Control
Sets the rate of background scrubbing for DRAM.
Options: Disabled / 80ns / 160ns / 320ns / 640ns / 1.28us / 2.56us / 5.12us /
10.2us / 20.5us / 41us / 81.9us / 163.8us /327.7us / 655.4us / 1.31ms / 2.62ms /
5.24ms / 10.49ms / 20.97ms / 42ms / 84ms
DCache ECC Scrub Control
Sets the rate of background scrubbing for the DCache.
Options: Disabled / 80ns / 160ns / 320ns / 640ns / 1.28us / 2.56us / 5.12us /
10.2us / 20.5us / 41us / 81.9us / 163.8us /327.7us / 655.4us / 1.31ms / 2.62ms /
5.24ms / 10.49ms / 20.97ms / 42ms / 84ms
L2 ECC Scrub Control
Sets the rate of background scrubbing for the L2 cache.
Options: Disabled / 80ns / 160ns / 320ns / 640ns / 1.28us / 2.56us / 5.12us /
10.2us / 20.5us / 41us / 81.9us / 163.8us /327.7us / 655.4us / 1.31ms / 2.62ms /
5.24ms / 10.49ms / 20.97ms / 42ms / 84ms
ECC Multibit Error Detection
Enable multibit ECC error detection.
Options: Disabled / Enabled