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Chapter 4 Power Management 9
26237C—May 2003 AMD Athlon™ XP Processor Model 10 Data Sheet
Preliminary Information
4 Power Management
This chapter describes the power management control system
of the AMD Athlon™ XP processor model 10. The power
management features of the processor are compliant with the
ACPI 1.0b and ACPI 2.0 specifications.
4.1 Power Management States
The AMD Athlon XP processor model 10 supports low-power
Halt and Stop Grant states. These states are used by advanced
configuration and power interface (ACPI) enabled operating
systems for processor power management.
Figure 3 shows the power management states of the processor.
The figure includes the ACPI “Cx” naming convention for these
states.
Figure 3. AMD Athlon™ XP Processor Model 10 Power Management States
C1
Halt
C0
Working
4
Execute HLT
SMI#, INTR, NMI, INIT#, RESET#
Incoming Probe
P
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STPCLK# asserted
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2
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3
C2
Stop Grant
Cache Snoopable
Incoming Probe
Probe Serviced
Probe
State
1
STPCLK# deasserted
(Read PLVL2 register
or throttling)
S1
Stop Grant
Cache Not Snoopable
Sleep
S
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#
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Note: The AMD Athlon
TM
System Bus is connected during the following states:
1) The Probe state
2) During transitions between the Halt state and the C2 Stop Grant state
3) During transitions between the C2 Stop Grant state and the Halt state
4) C0 Working state
Software transitions
Hardware transitions
Legend