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AMD Geode™ LX Processor/CS5536 Companion Device GeodeROM Porting Guide 15
4
Initialization 40680B
4.0Initialization
4.1 Processor Initialization
The AMD Geode™ LX processor contains many of the components normally found in system support chipsets.
GeodeROM must set up these components, including the DRAM controller, L1 cache controller, clock control, and PCI con-
troller as well as some proprietary systems like GeodeLink™ architecture.
This chapter contains descriptions and some pseudo code for Geode LX processor-specific code sequences in
GeodeROM. The modifications are grouped into CPU core initialization, DRAM controller initialization, GeodeLink interface
initialization, PCI bus initialization, and miscellaneous other initializations/changes.
4.1.1 Set Clocks and Reset
Register: GLCP_SYS_RSTPLL (GLCP MSR Address 4C000014h)
The LX processor has separate clocks for the CPU core and the GeodeLink interface. These clocks are derived from the
system PLL, which is driven by the SYSREF signal. At power-on, these clocks are determined by the strapped values of the
signals PW1, IRQ13, PW0, SUSPA#, and GNT[2:0]. The system should be running at a safe speed with the default set-
tings. Programming the appropriate fields in the GLCP_SYSRSTPLL register and then resetting the CPU will reclock the LX
processor.
The clocks are controlled through the COREDIV, COREMULT, MBDIV and GLIUMULT fields of GLCP_SYSRSTPLL as
illustrated in Figure 4-1. The SYSREF frequency will either be 33 MHz or 66 MHz. The frequency can be detected by read-
ing the BOOTSTRAPS field (bit 7).
The BIOS may initially assume a 33 MHz SYSREF. Then program the multipliers COREMULT and GLIUMULT to the
desired values. If a 66 MHz SYSREF is detected, the core and GLIU frequencies may be adjusted by setting COREDIV and
MBDIV. This will divide the frequencies in half.
Figure 4-1. Clock Control
COREMULT
COREDIV
GLCP_SYSRSTPLL[11]
GLIUMULT
MBDIV
GLCP_SYSRSTPLL[12]
SYSPLL
DOTREF
SYSREF
PCI Clock
CPU Clock
GLIU Clock
SDRAM Clock