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AMD Geode™ LX Processor/CS5536 Companion Device GeodeROM Porting Guide 19
Initialization
40680B
Registers:
CR0
RCONF MSRs: CPU Core MSR Address 00001808h-00001817h
Instruction Memory Configuration Register: CPU Core MSR Address 00001700h
Data Memory Configuration Register: CPU Core MSR Address 00001800h
Entry Conditions:
None
Procedure:
IF <L1 cache requested>
Setup the Default Region Configuration Properties and any other RCONFs required.
Write Cache Disable and Not Write-Through bits (bits [30:29]) in the CR0 register.
WBINVD
ENDIF
Note: See Figure 7-2 on page 31 for a pictorial presentation.
GLPCI Regions
The GLPCI has similar MSRs to the CPU Core Region Configuration registers for inbound transactions. These memory
regions control the memory hole from 6460 KB to 1 MB. Six flexible region MRSs are assigned: Memory Region 0 Configu-
ration (R0) through Memory Region 5 Configuration (R5).
Descriptor Allocation
Register: PHY_CAP (MSR Address GLIU0: 10000086h, GLIU1: 40000086h)
Each GLIU descriptor allocation is defined in the PHY_CAP register.
GLIU0 GLIU1
Descriptor MSR Address Memory Range Descriptor MSR Address Memory Range
P2D_BM[5:0] 10000020h P2D_BM[9:0] 40000020h
10000021h 40000021h
10000022h 40000022h
10000023h 40000023h
10000024h 40000024h
10000025h 40000025h
P2D_BMO[1:0] 10000026h 40000026h
10000027h 40000027h
P2D_R[0] 10000028h 40000028h
P2D_RO[3:0] 10000029h 40000029h
1000002Ah P2D_R[3:0] 4000002Ah
1000002Bh 4000002Bh
P2D_SC[0] 1000002Ch 4000002Ch
P2D_RSVD 1000002Dh -
1000003Fh
4000002Dh
P2D_SC[0] 4000002Eh
P2D_RSVD 4000002Eh -
4000003Fh