![](http://pdfasset.owneriq.net/5/98/5987ad6a-aecd-4b43-920a-3c9734d5cf45/5987ad6a-aecd-4b43-920a-3c9734d5cf45-bg46.png)
3-12
Chapter 3: BIOS setup
Chapter 3
DRAM WRITE to READ Delay [Auto]
Conguration options: [Auto] [1] – [15]
DRAM CKE Minimum pulse width [Auto]
Conguration options: [Auto] [1] – [15]
DRAM CAS# Write to Latency [Auto]
Conguration options: [Auto] [1] – [31]
RTL IOL control
DRAM RTL (CHA_R0D0) [Auto]
Conguration options: [Auto] [1] - [63]
DRAM RTL (CHA_R0D1) [Auto]
Conguration options: [Auto] [1] - [63]
DRAM RTL (CHA_R1D0) [Auto]
Conguration options: [Auto] [1] - [63]
DRAM RTL (CHA_R1D1) [Auto]
Conguration options: [Auto] [1] - [63]
DRAM RTL (CHB_R0D0) [Auto]
Conguration options: [Auto] [1] - [63]
DRAM RTL (CHB_R0D1) [Auto]
Conguration options: [Auto] [1] - [63]
DRAM RTL (CHB_R1D0) [Auto]
Conguration options: [Auto] [1] - [63]
DRAM RTL (CHB_R1D1) [Auto]
Conguration options: [Auto] [1] - [63]
DRAM IO-L (CHA_R0D0) [Auto]
Conguration options: [Auto] [1] - [15]
DRAM IO-L (CHA_R0D1) [Auto]
Conguration options: [Auto] [1] - [15]
DRAM IO-L (CHA_R1D0 [Auto]
Conguration options: [Auto] [1] - [15]
DRAM IO-L (CHA_R1D1 [Auto]
Conguration options: [Auto] [1] - [15]
DRAM IO-L (CHB_R0D0 [Auto]
Conguration options: [Auto] [1] - [15]
DRAM IO-L (CHB_R0D1) [Auto]
Conguration options: [Auto] [1] - [15]
DRAM IO-L (CHB_R1D0 [Auto]
Conguration options: [Auto] [1] - [15]
DRAM IO-L (CHB_R1D1 [Auto]
Conguration options: [Auto] [1] - [15]
Third Timings
tRDRD [Auto]
Conguration options: [Auto] [1] – [7]