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Schematic Diagrams
CLOCK GENERATOR B - 3
B.Schematic Diagrams
CLOCK GENERATOR
Sheet 2 of 40
CLOCK
GENERATOR
PCLKMINI1 17
PCLKH8 25
DREFSSCLK 6
MCHCLK
FS_B
SIOCLK14
Q14
2N3904
B
EC
PCLKFWH
Q13
2N7002
G
DS
R53 *10K/0402
C39
10UF/6.3V
R45 49.9_1%/0402
C416
1000PF
R281 49.9_1%/0402
PCLKFWH 24
R273 10K/0402
DREFCLK 6
FS_B
DREFCLK
P.U --> Pin35/36 For ITPCLK
ICHCLK14
PCLKSIO
PCLKSIO 24
CPUCLK2
0
PCLKICH
SATACLK
SRCCLK1
RN40
*4P2RX33
1
2 3
4
PM_STPPCI#11
+1.05VS
PCLKH8
R277
4.7K
FS_C
SRCCLK_VGA#
SRCCLK_VGA
U4
ICS954226
11
37
48
1
2 3
4
5
6
7
8
9
12
13
14
15
16
10
19
20
21
22
23
24
25
27
26
28
29
30
31
32
33
34
35
36
38
39
40
41
42
43
44
45
46
47
49
50
51 52
53
54
55
56
17
18
VDD48
VDDA
VDDREF
VDDPCI
GND PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PCICLK_F0(ITP_E)
PCICLK_F1(PCIE_E)
USB_48MHZ/FS_A
GND
DOT_96MHZ
DOT#96MHZ
FS_B/TST_MDE
VTT_PWRGD#/PD
SRCCLK_1
SRCCLK#1
VDDSRC
SRCCLK_2
SRCCLK#2
SRCCLK_3
SRCCLK#3
SATACLK#
SATACLK
VDDSRC
GND
SRCCLK#4
SRCCLK_4
SRCCLK#5(SATACLK#)
SRCCLK_5(SATACLK)
VDDSRC
C_ITPCLK#2/SRC#6
C_ITPCLK_2/SRC6
GNDA
IREF
CPUCLK#1
CPUCLK_1
VDDCPU
CPUCLK#0
CPUCLK_0
GND
SCLK
SDATA
X2
X1
GND REF0
REF1/FS_C/TST_SEL
CPU_STOP#
PCI/SRC_STOP#
PCICLK2/REQ_SEL
SRCCLK_0(LCDCLK)
SRCCLK#0(LCDCLK#)
SRCCLK_LAN 19
REQ_SEL
VDDCPU
R268 33/0402
VDD48
CPUCLK#
R52 33/0402
1
SIOCLK14 24
SRCCLK3
ITPCLK#
MCHCLK#
ICHCLK14
PM_STPCPU#11
SRCCLK_MCH# 6
PCLKPCM
R59 33/0402
+3VS
R46 49.9_1%/0402
R280
475_1%/0402
SRCCLK#5
R50 10K/0402
CPU_BSEL0 3,6
USBCLK48
SRCCLK_ICH
A
R269
10K
SRCCLK_SATA# 12
SRCCLK_MCH
SRCCLK_ICH#
DREFCLK#
RN4
4P2RX33
1
2 3
4
R69 49.9_1%/0402
SRCCLK_LAN
PCLKMINI1
RN39
*4P2RX33
1
2 3
4
R271
10K
SMBCLK
PCLKMINI2 17
R283 49.9_1%/0402
MCHCLK
ITPCLK
C49
1000PF
R62 49.9_1%/0402
L8
HCB1608K-121T25
1 2
SRCCLK0
SRCCLK4
+3VS
CPUCLK# 3
ITPCLK#
CPUCLK#1
R61 49.9_1%/0402
C48
*10PF
C407
*10PF
B
SRCCLK_VGA#
PCLKICH
R54 33/0402
R284 49.9_1%/0402
SRCCLK_ICH# 11
SRCCLK_LAN# 19
DREFCLK# 6
SRCCLK#2
R67 49.9_1%/0402
SRCCLK#1
R58 12.1_1%/0402
R66 49.9_1%/0402
L56
HCB1608K-121T25
12
CPUCLK 3
SRCCLK_ICH#
CPUCLK
C
C46
*10PF
C44
10P
+3VS
SRCCLK_VGA# 10
PCLKLAN
SRCCLK_LAN#
CPUCLK
Y1
14.318MHZ
12
C417
4.7UF/10V
PWROKICH10,11,12,26,27
MCHCLK#
R51 33/0402
RN6
4P2RX33
1
2 3
4
+3VS
DREFSSCLK
RN5
4P2RX33
1
2 3
4
C413
0.1UF_X7R
R279
2.2K
CPU_BSEL1 3,6
SRCCLK_VGA
SRCCLK_SATA#
DREF_CLK
CPUCLK1
FSBSEL
+3VS
SRCCLK_SATA 12
SRCCLK_MCH#
C52
*10PF
R275 *0/0402
R274
*0/0402
R270
1K
C50
1000PF
C40
10UF/6.3V
+3VS
SRCCLK_LAN
CLKEN#26
R64 49.9_1%/0402
DREF_CLK#
ICHCLK14 11
R55 10K/0402
533
SMBCLK8,9,11,18,19,21
PCLKMINI1
C51
*10PF
R276
*0/0402
C47
0.1UF_X7R
C408
0.1UF_X7R
R48 33/0402
CPUCLK#2
C42
0.1UF_X7R
O.P --> Pin17/18 For DOTCLK
C406
10UF/6.3V
DPG_VGATE6,11,12,26
SRCCLK_ICH 11
USBCLK48 11
R278
1K
USBCLK48
REQ_SEL
400
DREFSSCLK# 6
DREFSSCLK#
PCLKFWH
PCLKH8
CPUCLK0
SRCCLK_SATA
R63 49.9_1%/0402
C45
*10PF
RN7
4P2RX33
1
2 3
4
L58
HCB3216K-800T30
P.U --> Pin17/18 For SRCCLK
C53
*10PF
C54
*10PF
+3VS
ITPCLK# 3
SRCCLK_VGA 10
PCLKPCM
C409
0.1UF_X7R
1
PM_STPPCI#
R515 12.1_1%/0402
R272
0/0402
R49 33/0402
SRCCLK_LAN#
C414
1000PF
R68 49.9_1%/0402
SRCCLK2
C411
0.1UF_X7R
MCHCLK# 5
C55
*10PF
RN2
4P2RX33
1
2 3
4
+3VS
ITPCLK 3
PCLKLAN 18
1
PCLKMINI2
R60 49.9_1%/0402
R282 49.9_1%/0402
Iref=2.32mA
VTT_PWRGD#
R57 12.1_1%/0402
SRCCLK_SATA#
C415
0.1UF_X7R
PCLKICH 11
MCHCLK 5
PCLKSIO
SRCCLK_SATA
SRCCLK#0
C41
0.1UF_X7R
0
SRCCLK_MCH 6
SIOCLK14
SRCCLK_MCH#
PCLKMINI2
P.D --> Pin35/36 For SRCCLK
CPUCLK#0
SRCCLK5
C410
0.1UF_X7R
ITPCLK
SATACLK#
SRCCLK_MCH
RN1
*4P2RX33
1
2 3
4
PCLKPCM 15
C670
*10PF
CPUCLK#
R65 49.9_1%/0402
FS_A
RN8
4P2RX33
1
2 3
4
+3VS
PM_STPCPU#
FS_C
0
R56 12.1_1%/0402
C43
10P
SMBDATA8,9,11,18,19,21
FS_A
L7
HCB1608K-121T25
1 2
+
C412
47UF/6.3V
12
SRCCLK_ICH
SRCCLK#3
SMBDATA
SRCCLK#4
RN3
4P2RX33
1
2 3
4