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Schematic Diagrams
Cantiga 1/6 - Host B - 5
B.Schematic Diagrams
Cantiga 1/6 - Host
MC H_BS EL2 [5]
H_D#52
R29
H_ ADST B#0 [2]
H_D#3
H_D#42
C353
0.1U _10V_X7R_04
1.05VS
H_DINV#2 [2]
H_D#20
24.9_1%_04
H_ BREQ# [2]
1.05VS
MC H_BS EL0 [5]
H_A#32
H_D#14
H_D#50
H_D#54
H_A#3
H_A#8
H_D#37
R218
2K_1%_04
H_DINV#3 [2]
H_D#51
H_A#24
H_D#27
H_A#19
266
16.9_1%_04
CPU_ BSEL0[2,18]
H_D#19
R204
1K _04
R202
1K_04
R212 221_1%_04
H_DSTBP#1 [2]
H_A#23
H_A#34
H_D#33
H_A#6
R208
* 56_04
H_D#39
H_A#29
H_D#25
H_D#18
H_DSTBN#3 [2]
H_D#43
H_D#36
H_DEFER# [2]
R206
1K _04
H_DPWR# [ 2]
H_REQ#4 [2]
L
1.05VS
H
H_HIT#[2]
1.05VS
H_DRDY# [2]
H_DSTBP#2 [2]
H_REQ#1 [2]
H_A#27
H_CPURST#[2]
H_D#13
CPU_BSEL1
L
H
CL K_BSEL2 [2,1 8]
H_D#17
H_D#47
H_D#30
H_D#56
H_D#45
H_DSTBP#3 [2]
H_DINV#1 [2]
1.05VS[2,3,5,7,8,13,16,29]
H_D#46
H_D#61
H_A#20
H_D#32
H_A#21
CPU_BSEL0
CLK_MCH_BCLK# [ 18]
H_D#63
H_A#13
H_A#33
H
H_A#9
H_A#18
L
H_DINV#0 [2]
H_REQ#2 [2]
H_D#59
H_ ADST B#1 [2]
H_CPUSLP#[2]
H_D#55
R213
H_REQ#3 [2]
H_HITM# [ 2]
H_DSTBN#2 [2]
H_D#38
CPU_BSEL2
H_VREF
H_ ADS# [2]
H_D#12
L
H_DSTBN#1 [2]
H_A#16
H_D#6
H_D#53
H_A#14
C363
0.1U _10V_X7R _04
H_TRDY#[2]
H_D#22
H_D#8
H_A#15
H_D#29
166
CPU
H_D#16
H_D#49
H_D#60
H_D#23
H_D#31
CL K_BSEL1 [2,1 8]
H_RS#2 [2]
H_D#41
H_A#10
CL K_BSEL0 [2,1 8]
H_REQ#0 [2]
H_D#35
R29 24. 9_1%_0 4
200
100_1%_04
H_D#1
H_BPRI# [2]
R203
1K _04
1.05VS
H_A#28
H_A#11
H_D#58
H_A#22
H_LOCK# [2]
H_D#0
H_A#30
C366
0.1U _10V_X7R_04
H_A#26
R219 1K_1%_04
12mils
H_BNR#[2]
H_D#62
H_D#7
H_A#35
HOST
U15A
CANTIGA-EB88C TGM
P1 6
R16
N17
M13
E1 7
P1 7
F17
G20
B1 9
J16
E2 0
H16
J20
L17
A1 7
B1 7
L16
C21
J17
H20
A1 4
B1 8
K1 7
C15
F16
H13
C18
M16
J13
H12
B1 6
G17
A9
F11
G12
AH6
C12
AH7
F2
F13
B1 3
G8
M9
L6
N10
AA8
AA2
AE11
D4
H3
B1 0
M11
J1
J2
N12
J6
P2
L2
R2
N9
F8
M5
J3
N2
R1
N5
N6
P1 3
N8
L7
E6
M3
Y3
AD1 4
Y6
Y10
Y12
Y14
Y7
W2
G2
Y9
AA13
AA9
AA11
AD1 1
AD1 0
AD1 3
AE12
AE9
H6
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
H2
AE8
AG 2
AD6
F6
E9
J8
L3
Y13
Y1
J11
F9
L10
M7
AA5
AE6
L9
M8
AA6
AE5
A1 1
B1 1
C9
H9
E1 2
H11
B1 5
K1 3
B1 4
B2 0
F21
K2 1
L20
C5
E1 1
E3
B6
F12
C8
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_3
H_A#_30
H_A#_31
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BP RI#
H_ BREQ#
HPLL_CLK #
H_CPURST#
HPLL_CLK
H_D#_0
H_REQ #_2
H_REQ #_3
H_D#_1
H_D#_10
H_D#_20
H_D#_30
H_D#_40
H_D#_50
H_D#_60
H_D#_8
H_D#_9
H_DBSY#
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_2
H_D
#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_3
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_4
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_5
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_6
H_D#_61
H_D#_62
H_D#_63
H_D#_7
H_DEFER#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DPW R#
H_DRDY#
H_DST BN# _0
H_DST BN# _1
H_DST BN# _2
H_DST BN# _3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_AVREF
H_DVREF
H_TRDY#
H_HIT#
H_HITM#
H_LOCK#
H_REQ #_0
H_REQ #_1
H_REQ #_4
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_SWING
H_CPUSLP#
H_RCOMP
H_RS#_0
H_RS#_1
H_RS#_2
H_A#31
H_D#40
Dual Core
CPU_ BSEL2[2,18]
H_DSTBP#0 [2]
H_D#57
H_SWING
H_D#21
H_D#24
12mils
H_D#10
H_D#28
L
CLK_MCH_BCLK [18]
H_D#9
H_A#4
H_D#34
H_A#12
L
CPU_BSEL[2:0] (FSB) DAEFULT SETTING
Quad Core
H_A#17
H_DBSY#[2]
H_DSTBN#0 [2]
H_D#26
H_D#[63: 0][2]
H_A#5
H_D#44
MC H_BS EL1 [5]
H_RS#0 [2]
H_A#25
R213
100_1%_04
75_1%_04
CPU_ BSEL1[2,18]
H_D#4
H_A#[35: 3][2]
H_A#7
H_D#11
H_D#2
R205
1K _04
H_RS#1 [2]
H_D#15
H_D#48
H_D#5
R207
1K _04
Sheet 4 of 40
Cantiga 1/6 - Host