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ADVANCE
CY14B108L, CY14B108N
Document Number: 001-45523 Rev. *A Page 12 of 20
Figure 8. SRAM Write Cycle #2: CE
Controlled
[13, 21, 22, 23]
Figure 9. AutoStore or Power Up RECALL
[24]
Note
24.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V
SWITCH
.
Switching Waveforms (continued)
t
WC
ADDRESS
t
SA
t
SCE
t
HA
t
AW
t
PWE
t
SD
t
HD
CE
WE
DATA IN
DATA OUT
HIGH IMPEDANCE
DATA VALID
BHE , BLE
t
BW
V
CC
V
SWITCH
t
STORE
t
STORE
t
HRECALL
t
HRECALL
AutoStore
POWER-UP RECALL
Read & Write Inhibited
STORE occurs only
if a SRAM write
has happened
No STORE occurs
without atleast one
SRAM write
t
VCCRISE
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