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CY62136EV30
MoBL
®
Document #: 38-05569 Rev. *B Page 5 of 12
Switching Characteristics Over the Operating Range
[10, 11, 12, 13]
Parameter Description
45 ns
UnitMin. Max.
Read Cycle
t
RC
Read Cycle Time 45 ns
t
AA
Address to Data Valid 45 ns
t
OHA
Data Hold from Address Change 10 ns
t
ACE
CE LOW to Data Valid 45 ns
t
DOE
OE LOW to Data Valid 22 ns
t
LZOE
OE LOW to LOW Z
[11]
5ns
t
HZOE
OE HIGH to High Z
[11, 12]
18 ns
t
LZCE
CE LOW to Low Z
[11]
10 ns
t
HZCE
CE HIGH to High Z
[11, 12]
18 ns
t
PU
CE LOW to Power-Up 0 ns
t
PD
CE HIGH to Power-Down 45 ns
t
DBE
BLE/BHE LOW to Data Valid 22 ns
t
LZBE
BLE/BHE LOW to Low Z
[11]
5ns
t
HZBE
BLE/BHE HIGH to HIGH Z
[11, 12]
18 ns
Write Cycle
[13]
t
WC
Write Cycle Time 45 ns
t
SCE
CE LOW to Write End 35 ns
t
AW
Address Set-Up to Write End 35 ns
t
HA
Address Hold from Write End 0 ns
t
SA
Address Set-Up to Write Start 0 ns
t
PWE
WE Pulse Width 35 ns
t
BW
BLE/BHE LOW to Write End 35 ns
t
SD
Data Set-Up to Write End 25 ns
t
HD
Data Hold from Write End 0 ns
t
HZWE
WE LOW to High-Z
[11, 12]
18 ns
t
LZWE
WE HIGH to Low-Z
[11]
10 ns
Notes:
10.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
CC(typ)
/2, input
pulse levels of 0 to V
CC(typ.)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
11.At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
12.t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedence state.
13.The internal Write time of the memory is defined by the overlap of WE
, CE
= V
IL
, BHE and/or BLE = V
IL
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write.
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