Cypress CY7C1298H Computer Monitor User Manual

1-Mbit (64K x 18) Pipelined DCD Sync SRAM
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document #: 38-05665 Rev. *B Revised July 5, 2006
Registered inputs and outputs for pipelined operation
Optimal for performance (Double-Cycle deselect)
Depth expansion without wait state
64K × 18-bit common I/O architecture
3.3V core power supply (V
2.5V/3.3V I/O power supply (V
Fast clock-to-output times
3.5 ns (for 166-MHz device)
Provide high-performance 3-1-1-1 access rate
User-selectable burst counter supporting Intel
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous Output Enable
Available in JEDEC-standard lead-free 100-Pin TQFP
“ZZ” Sleep Mode option
Functional Description
The CY7C1298H SRAM integrates 64K x 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
), depth-expansion Chip Enables (CE
and CE
), Burst
Control inputs (ADSC
, ADSP, and ADV), Write Enables
, and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE
) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP
) or
Address Strobe Controller (ADSC
) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as
controlled by the byte write control inputs. GW
active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
The CY7C1298H operates from a +3.3V core power supply
while all outputs operate either with a +2.5V or +3.3V supply.
All inputs and outputs are JEDEC-standard
Selection Guide
166 MHz 133 MHz Unit
Maximum Access Time 3.5 4.0 ns
Maximum Operating Current 240 225 mA
Maximum CMOS Standby Current 40 40 mA
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on
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