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CY7C1302DV25
Document #: 38-05625 Rev. *A Page 15 of 18
Output Times
t
CO
t
CHQV
C/C Clock Rise (or K/K in single clock mode) to Data Valid 2.5 ns
t
DOH
t
CHQX
Data Output Hold after Output C/C Clock Rise (Active to Active) 1.2 ns
t
CHZ
t
CHZ
Clock (C and C) Rise to High-Z (Active to High-Z)
[23, 24]
2.5 ns
t
CLZ
t
CLZ
Clock (C and C) Rise to Low-Z
[23, 24]
1.2 ns
Notes:
23.t
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
24.At any given voltage and temperature t
CHZ
is less than t
CLZ
and, t
CHZ
less than t
CO
.
Switching Characteristics Over the Operating Range (continued)
[21]
Cypress
Parameter
Consortium
Parameter Description
167 MHz
UnitMin. Max.
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