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CY7C1361C
CY7C1363C
Document #: 38-05541 Rev. *F Page 15 of 31
3.3V TAP AC Test Conditions
Input pulse levels ................................................ V
SS
to 3.3V
Input rise and fall times................................................... 1 ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Test Conditions
Input pulse levels.................................................V
SS
to 2.5V
Input rise and fall time .....................................................1 ns
Input timing reference levels......................................... 1.25V
Output reference levels ................................................ 1.25V
Test load termination supply voltage ............................ 1.25V
2.5V TAP AC Output Load Equivalent
T
DO
1.5V
20p
F
Z = 50Ω
O
50Ω
T
DO
1.25V
20p
F
Z = 50Ω
O
50Ω
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)
[11]
Parameter Description Description Conditions Min. Max. Unit
V
OH1
Output HIGH Voltage I
OH
= –4.0 mA V
DDQ
= 3.3V 2.4 V
I
OH
= –1.0 mA V
DDQ
= 2.5V 2.0 V
V
OH2
Output HIGH Voltage I
OH
= –100 µA V
DDQ
= 3.3V 2.9 V
V
DDQ
= 2.5V 2.1 V
V
OL1
Output LOW Voltage I
OL
= 8.0 mA V
DDQ
= 3.3V 0.4 V
I
OL
= 8.0 mA V
DDQ
= 2.5V 0.4 V
V
OL2
Output LOW Voltage I
OL
= 100 µA V
DDQ
= 3.3V 0.2 V
V
DDQ
= 2.5V 0.2 V
V
IH
Input HIGH Voltage V
DDQ
= 3.3V 2.0 V
DD
+ 0.3 V
V
DDQ
= 2.5V 1.7 V
DD
+ 0.3 V
V
IL
Input LOW Voltage V
DDQ
= 3.3V –0.5 0.7 V
V
DDQ
= 2.5V –0.3 0.7 V
I
X
Input Load Current GND < V
IN
< V
DDQ
–5 5 µA
Identification Register Definitions
Instruction Field
CY7C1361C
(256K x36)
CY7C1363C
(512K x18) Description
Revision Number (31:29) 000 000 Describes the version number.
Device Depth (28:24)
[12]
01011 01011 Reserved for Internal Use
Device Width (23:18) 119-BGA 101001 101001 Defines memory type and architecture
Device Width (23:18) 165-FBGA 000001 000001 Defines memory type and architecture
Cypress Device ID (17:12) 100110 010110 Defines width and density
Cypress JEDEC ID Code (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor.
ID Register Presence Indicator (0) 1 1 Indicates the presence of an ID register.
Notes:
11.All voltages referenced to V
SS
(GND).
12.Bit #24 is “1” in the Register Definitions for both 2.5V and 3.3V versions of this device.
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