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CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Document #: 38-05547 Rev. *E Page 22 of 28
Read/Write Cycle Timing
[25, 27, 28]
Timing Diagrams (continued)
t
CYC
t
CL
CLK
t
ADH
t
ADS
ADDRESS
t
CH
t
AH
t
AS
A2
t
CEH
t
CES
Single WRITE
D(A3)
A3 A4
BURST READ
Back-to-Back READs
High-Z
Q(A2)
Q(A4) Q(A4+1)
Q(A4+2)
Q(A4+3)
t
WEH
t
WES
t
OEHZ
t
DH
t
DS
t
CDV
t
OELZ
A1 A5 A6
D(A5) D(A6)
Q(A1)
Back-to-Back
WRITEs
DON’T CARE UNDEFINED
ADSP
ADSC
BWE, BW
X
CE
ADV
OE
Data In (D)
Data Out (Q)
Notes
27.The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP
or ADSC.
28.GW
is HIGH.
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