CY7C1381DV25, CY7C1381FV25
CY7C1383DV25, CY7C1383FV25
Document #: 38-05547 Rev. *E Page 23 of 28
ZZ Mode Timing
[29, 30]
Timing Diagrams (continued)
t
ZZ
I
SUPPLY
CLK
ZZ
t
ZZREC
ALL INPUTS
(except ZZ)
DON’T CARE
I
DDZZ
t
ZZI
t
RZZI
Outputs (Q)
High-Z
DESELECT or READ Only
Notes
29.Device must be deselected when entering ZZ sleep mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
30.DQs are in high-Z when exiting ZZ sleep mode.
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