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CY7C1380C
CY7C1382C
Document #: 38-05237 Rev. *D Page 13 of 36
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the
“sleep” mode. CE
1
, CE
2
, CE
3
, ADSP, and ADSC must
remain inactive for the duration of t
ZZREC
after the ZZ input
returns LOW
.
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
I
DDZZ
Snooze mode standby current ZZ > V
DD
– 0.2V 60mA mA
t
ZZS
Device operation to ZZ ZZ > V
DD
– 0.2V 2t
CYC
ns
t
ZZREC
ZZ recovery time ZZ < 0.2V 2t
CYC
ns
t
ZZI
ZZ Active to snooze current This parameter is sampled 2t
CYC
ns
t
RZZI
ZZ Inactive to exit snooze current This parameter is sampled 0 ns
Truth Table
[ 3, 4, 5, 6, 7, 8]
Operation Add. Used
CE
1
CE
2
CE
3
ZZ ADSP ADSC ADV
WRITE
OE
CLK DQ
Deselect Cycle,Power Down None H X X L X L X X X L-H Tri-State
Deselect Cycle,Power Down None L L X L L X X X X L-H Tri-State
Deselect Cycle,Power Down None L X H L L X X X X L-H Tri-State
Deselect Cycle,Power Down None L L X L H L X X X L-H Tri-State
Deselect Cycle,Power Down None L X H L H L X X X L-H Tri-State
Snooze Mode,Power Down None X X X H X X X X X X Tri-State
READ Cycle, Begin Burst External L H L L L X X X L L-H Q
READ Cycle, Begin Burst External L H L L L X X X H L-H Tri-State
WRITE Cycle, Begin Burst External L H L L H L X L X L-H D
READ Cycle, Begin Burst External L H L L H L X H L L-H Q
READ Cycle, Begin Burst External L H L L H L X H H L-H Tri-State
READ Cycle, Continue Burst Next X X X L H H L H L L-H Q
READ Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State
READ Cycle, Continue Burst Next H X X L X H L H L L-H Q
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