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CY7C138, CY7C139
Document #: 38-06037 Rev. *D Page 10 of 17
Figure 11. Write Timing with Busy Input (M/S=LOW)
Notes
27.I/O
0R
= I/O
0L
= LOW (request semaphore); CE
R
= CE
L
= HIGH
28.Semaphores are reset (available to both ports) at cycle start.
29.If t
SPS
is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
Figure 12. Busy Timing Diagram No. 1 (CE Arbitration)
[30]
Switching Waveforms (continued)
VALID
t
DDD
t
WDD
MATCH
MATCH
R/W
R
DATA IN
R
DATA
OUTL
t
WC
ADDRESS
R
t
PWE
VALID
t
SD
t
HD
ADDRESS
L
t
PS
t
BLA
t
BHA
t
BDD
BUSY
L
t
PWE
R/W
BUSY
t
WB
t
WH
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