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CY7C1440AV33
CY7C1442AV33
CY7C1446AV33
Document #: 38-05383 Rev. *E Page 7 of 31
CE
2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and CE
3
to select/deselect the device. CE
2
is sampled only when a new external
address is loaded.
CE
3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and
CE
2
to select/deselect the device. Not available for AJ package version. Not
connected for BGA. Where referenced, CE
3
is assumed active throughout this document
for BGA. CE
3
is sampled only when a new external address is loaded.
OE
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated,
and act as input data pins. OE is masked during the first clock of a read cycle when emerging
from a deselected state.
ADV Input-
Synchronous
Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted,
it automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP
is recognized. ASDP is ignored when CE
1
is deasserted HIGH.
ADSC
Input-
Synchronous
Address Strobe from Controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP
is recognized.
ZZ Input-
Asynchronous
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal pull-down.
DQs, DQP
X
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous
clock rise of the
read cycle. The direction of the pins is controlled by OE
. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and DQP
X
are placed in a tri-state condition.
V
DD
Power Supply Power supply inputs to the core of the device.
V
SS
Ground Ground for the core of the device.
V
SSQ
I/O Ground Ground for the I/O circuitry.
V
DDQ
I/O Power Supply Power supply for the I/O circuitry.
MODE Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V
DD
or left floating selects interleaved burst sequence. This is a strap pin and should remain
static during device operation. Mode Pin has an internal pull-up.
TDO JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not being utilized, this pin should be disconnected. This pin is not available
on TQFP packages.
TDI JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be disconnected or connected to V
DD
. This pin is not
available on TQFP packages.
TMS JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be disconnected or connected to V
DD
. This pin is not
available on TQFP packages.
TCK JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must
be connected to V
SS
. This pin is not available on TQFP packages.
NC – No Connects. Not internally connected to the die
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
– No Connects. Not internally connected to the die. NC/72M, NC/144M, NC/288M, NC/576M
and NC/1G are address expansion pins are not internally connected to the die.
Pin Definitions (continued)
Name I/O Description
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