Filter
Top Products
CY7C1480V25
CY7C1482V25
CY7C1486V25
Document #: 38-05282 Rev. *H Page 15 of 32
2.5V TAP AC Test Conditions
Input pulse levels ................................................ V
SS
to 2.5V
Input rise and fall time..................................................... 1 ns
Input timing reference levels.........................................1.25V
Output reference levels.................................................1.25V
Test load termination supply voltage.............................1.25V
1.8V TAP AC Test Conditions
Input pulse levels..................................... 0.2V to V
DDQ
– 0.2
Input rise and fall time .....................................................1 ns
Input timing reference levels........................................... 0.9V
Output reference levels .................................................. 0.9V
Test load termination supply voltage .............................. 0.9V
2.5V TAP AC Output Load Equivalent
TDO
1.25V
20pF
Z = 50Ω
O
50Ω
1.8V TAP AC Output Load Equivalent
TDO
0.9V
20pF
Z = 50Ω
O
50Ω
TAP DC Electrical Characteristics And Operating Conditions
(0°C < T
A
< +70°C; V
DD
= 2.5V ±0.125V unless otherwise noted)
[11]
Parameter Description Test Conditions Min Max Unit
V
OH1
Output HIGH Voltage I
OH
= –1.0 mA V
DDQ
= 2.5V 1.7 V
V
OH2
Output HIGH Voltage I
OH
= –100 µAV
DDQ
= 2.5V 2.1 V
V
DDQ
= 1.8V 1.6 V
V
OL1
Output LOW Voltage I
OL
= 1.0 mA V
DDQ
= 2.5V 0.4 V
V
OL2
Output LOW Voltage I
OL
= 100 µAV
DDQ
= 2.5V 0.2 V
V
DDQ
= 1.8V 0.2 V
V
IH
Input HIGH Voltage V
DDQ
= 2.5V 1.7 V
DD
+ 0.3 V
V
DDQ
= 1.8V 1.26 V
DD
+ 0.3 V
V
IL
Input LOW Voltage V
DDQ
= 2.5V –0.3 0.7 V
V
DDQ
= 1.8V –0.3 0.36 V
I
X
Input Load Current GND ≤ V
I
≤ V
DDQ
–5 5 µA
Identification Register Definitions
Instruction Field
CY7C1480V25
(2M x36)
CY7C1482V25
(4M x 18)
CY7C1486V25
(1M x72)
Description
Revision Number (31:29) 000 000 000 Describes the version number
Device Depth (28:24) 01011 01011 01011 Reserved for internal use
Architecture/Memory
Type(23:18)
000000 000000 000000 Defines memory type and
architecture
Bus Width/Density(17:12) 100100 010100 110100 Defines width and density
Cypress JEDEC ID Code
(11:1)
00000110100 00000110100 00000110100 Enables unique identification
of SRAM vendor
ID Register Presence
Indicator (0)
1 1 1 Indicates the presence of an
ID register
Note
11. All voltages referenced to V
SS
(GND).
[+] Feedback