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CY7C1480V25
CY7C1482V25
CY7C1486V25
Document #: 38-05282 Rev. *H Page 21 of 32
Notes
15.Timing reference level is 1.25V when V
DDQ
= 2.5V and is 0.9V when V
DDQ
= 1.8V.
16.Test conditions shown in (a) of “AC Test Loads and Waveforms” on page 20 unless otherwise noted.
17.This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
(minimum) initially before a read or write operation
can be initiated.
18.t
CHZ
, t
CLZ
, t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms. Transition is measured ±200 mV from
steady-state voltage.
19.At any possible voltage and temperature, t
OEHZ
is less than t
OELZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z before Low-Z under the same system conditions.
20.This parameter is sampled and not 100% tested.
Switching Characteristics Over the Operating Range
[15, 16]
Parameter Description
250 MHz 200 MHz 167 MHz
Unit
Min. Max. Min. Max. Min. Max.
t
POWER
V
DD
(Typical) to the first access
[17]
111ms
Clock
t
CYC
Clock Cycle Time 4.0 5.0 6.0 ns
t
CH
Clock HIGH 2.0 2.0 2.4 ns
t
CL
Clock LOW 2.0 2.0 2.4 ns
Output Times
t
CO
Data Output Valid After CLK Rise 3.0 3.0 3.4 ns
t
DOH
Data Output Hold After CLK Rise 1.3 1.3 1.5 ns
t
CLZ
Clock to Low-Z
[18, 19, 20]
1.3 1.3 1.5 ns
t
CHZ
Clock to High-Z
[18, 19, 20]
3.0 3.0 3.4 ns
t
OEV
OE LOW to Output Valid 3.0 3.0 3.4 ns
t
OELZ
OE LOW to Output Low-Z
[18, 19, 20]
000ns
t
OEHZ
OE HIGH to Output High-Z
[18, 19, 20]
3.0 3.0 3.4 ns
Setup Times
t
AS
Address Setup Before CLK Rise 1.4 1.4 1.5 ns
t
ADS
ADSC, ADSP Setup Before CLK Rise 1.4 1.4 1.5 ns
t
ADVS
ADV Setup Before CLK Rise 1.4 1.4 1.5 ns
t
WES
GW, BWE, BW
X
Setup Before CLK Rise 1.4 1.4 1.5 ns
t
DS
Data Input Setup Before CLK Rise 1.4 1.4 1.5 ns
t
CES
Chip Enable Setup Before CLK Rise 1.4 1.4 1.5 ns
Hold Times
t
AH
Address Hold After CLK Rise 0.4 0.4 0.5 ns
t
ADH
ADSP, ADSC Hold After CLK Rise 0.4 0.4 0.5 ns
t
ADVH
ADV Hold After CLK Rise 0.4 0.4 0.5 ns
t
WEH
GW, BWE, BW
X
Hold After CLK Rise 0.4 0.4 0.5 ns
t
DH
Data Input Hold After CLK Rise 0.4 0.4 0.5 ns
t
CEH
Chip Enable Hold After CLK Rise 0.4 0.4 0.5 ns
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