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CY7C65113C
Document #: 38-08002 Rev. *D Page 20 of 49
Bit [7:0]: Timer lower eight bits.
Bit [3:0]: Timer higher nibble
Bit [7:4]: Reserved.
11.0 I
2
C Configuration Register
Internal hardware supports communication with external devices through an I
2
C-compatible interface. I
2
C-compatible function is
discussed in detail in Section 12.0.
[3]
The I
2
C Position bit (Bit 7, Figure 11-1) and I
2
C Port Width bit (Bit 1, Figure 11-1) select the
locations of the SCL (clock) and SDA (data) pins on Port 1 as shown in Table 11-1. These bits are cleared on reset. When the
GPIO is configured for I
2
C function, the internal pull ups on the pins are disabled. Addition of an external weak pull-up resistors
on SCL and SDA is recommended.
.
Timer LSB Address 0x24
Bit # 76543210
Bit Name Timer Bit 7 TimerBit 6 Timer Bit 5 Timer Bit 4 Timer Bit 3 Timer Bit 2 Timer Bit 1 Timer Bit 0
Read/WriteRRRRRRRR
Reset 00000000
Figure 10-1. Timer LSB Register
Timer MSB Address 0x25
Bit # 76543210
Bit Name Reserved Reserved Reserved Reserved Timer Bit 11 Timer Bit 10 Timer Bit 9 Timer Bit 8
Read/Write – – – – R R R R
Reset 00000000
Figure 10-2. Timer MSB Register
I
2
C Configuration Address 0x09
Bit # 76543210
Bit Name I
2
C Position Reserved Reserved Reserved Reserved Reserved I
2
C Port
Width
Reserved
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 00000000
Figure 11-1. I
2
C Configuration Register
Table 11-1. I
2
C Port Configuration
I
2
C Position (Bit7, Figure 11-1)I
2
C Port Width (Bit1, Figure 11-1)I
2
C Position
00I
2
C on P1[1:0], 0:SCL, 1:SDA
10 9 7856 432
1 MHz clock
1.024-ms interrupt
128-
µs interrupt
To Timer Registers
8
1 011
L1 L0L2L3
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 10-3. Timer Block Diagram
Note:
3. I
2
C-compatible function must be separately enabled, as described in Section 12.0.
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