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CY8C23433, CY8C23533
Document Number: 001-44369 Rev. *B Page 33 of 37
AC I
2
C Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to
5.25V and -40°C ≤ T
A
≤ 85°C, or 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C
and are for design guidance only.
Figure 17. Definition for Timing for Fast/Standard Mode on the I
2
C Bus
Figure 18.
Table 36. AC Characteristics of the I
2
C SDA and SCL Pins for Vdd > 3.0V
Symbol Description
Standard Mode Fast Mode
Units
Min Max Min Max
F
SCLI2C
SCL Clock Frequency 0 100 0 400 kHz
T
HDSTAI2C
Hold Time (repeated) START Condition. After this period, the
first clock pulse is generated.
4.0 –0.6– μs
T
LOWI2C
LOW Period of the SCL Clock 4.7 –1.3– μs
T
HIGHI2C
HIGH Period of the SCL Clock 4.0 –0.6– μs
T
SUSTAI2C
Setup Time for a Repeated START Condition 4.7 –0.6– μs
T
HDDATI2C
Data Hold Time 0 –0– μs
T
SUDATI2C
Data Setup Time 250 –
100
[21]
–ns
T
SUSTOI2C
Setup Time for STOP Condition 4.0 –0.6– μs
T
BUFI2C
Bus Free Time Between a STOP and START Condition 4.7 –1.3– μs
T
SPI2C
Pulse Width of spikes are suppressed by the input filter. – –050ns
Table 37. AC Characteristics of the I
2
C SDA and SCL Pins for Vdd < 3.0V (Fast Mode Not Supported)
Symbol Description
Standard Mode Fast Mode
Units
Min Max Min Max
F
SCLI2C
SCL Clock Frequency 0 100 – –kHz
T
HDSTAI2C
Hold Time (repeated) START Condition. After this period, the
first clock pulse is generated.
4.0 – – – μs
T
LOWI2C
LOW Period of the SCL Clock 4.7 – – – μs
T
HIGHI2C
HIGH Period of the SCL Clock 4.0 – – – μs
T
SUSTAI2C
Setup Time for a Repeated START Condition 4.7 – – – μs
T
HDDATI2C
Data Hold Time 0 – – – μs
T
SUDATI2C
Data Setup Time 250 – – –ns
T
SUSTOI2C
Setup Time for STOP Condition 4.0 – – – μs
T
BUFI2C
Bus Free Time Between a STOP and START Condition 4.7 – – – μs
T
SPI2C
Pulse Width of spikes are suppressed by the input filter. – – – –ns
SDA
SCL
S
Sr SP
T
BUFI2C
T
SPI2C
T
HDSTAI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
Note
21.A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t
SU;DAT
≥ 250 ns must then be met. This is automatically the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line t
rmax
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
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