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CYD01S36V
CYD02S36V/36VA/CYD04S36V
CYD09S36V/CYD18S36V
Document Number: 38-06076 Rev. *G Page 22 of 28
Figure 16. Left_Port (L_Port) Write to Right_Port (R_Port) Read
[50, 51, 52]
Notes
50.CE
0
= OE = ADS = CNTEN = BE0 – BE3 = LOW; CE
1
= CNTRST = MRST = CNT/MSK = HIGH.
51.This timing is valid when one port is writing, and other port is reading the same location at the same time. If t
CCS
is violated, indeterminate data is Read out.
52.If t
CCS
< minimum specified value, then R_Port Reads the most recent data (written by L_Port) only (2 * t
CYC2
+ t
CD2
) after the rising edge of R_Port's clock. If t
CCS
>
minimum specified value, then R_Port Reads the most recent data (written by L_Port) (t
CYC2
+ t
CD2
) after the rising edge of R_Port's clock.
Switching Waveforms (continued)
t
SA
t
HA
t
SW
t
HW
t
CH2
t
CL2
t
CYC2
CLK
L
R/W
L
A
n
D
n
t
CKHZ
t
HD
t
SA
A
n
t
HA
Q
n
t
DC
t
CCS
t
SD
t
CKLZ
t
CH2
t
CL2
t
CYC2
t
CD2
L_PORT
ADDRESS
L_PORT
DATA
IN
CLK
R
R/W
R
R_PORT
ADDRESS
R_PORT
DATA
OUT
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