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Document #: 001-01638 Rev. *E Page 19 of 26
Write Cycle No.1: R/W Controlled Timing
[41, 42, 43, 44, 45, 46]
Write Cycle No. 2: CE Controlled Timing
[41, 42, 43, 48]
Notes:
43.t
HA
is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
44.If OE
is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or (t
HZWE
+ t
SD
) to allow the I/O drivers to turn off and data to
be placed on the bus for the required t
SD
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified t
PWE
.
45.To access RAM, CE
= V
IL
, SEM = V
IH
.
46.To access upper byte, CE
= V
IL
, UB = V
IL
, SEM = V
IH
.
To access lower byte, CE
= V
IL
, LB = V
IL
, SEM = V
IH
.
47.Transition is measured ±0 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
48.During this period, the I/O pins are in the output state, and input signals must not be applied.
Switching Waveforms (continued)
t
AW
t
WC
t
PWE
t
HD
t
SD
t
HA
CE
R/W
OE
DATA OUT
DATA IN
ADDRESS
t
HZOE
t
SA
t
HZWE
t
LZWE
[47]
[47]
[44]
[45, 46]
NOTE 48
NOTE 48
t
AW
t
WC
t
SCE
t
HD
t
SD
t
HA
CE
R/W
DATA IN
ADDRESS
t
SA
[45, 46]
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