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• Up to two quad-rank RDIMMs and up to three dual- or single-rank RDIMMs can be populated per channel. When a
quad-rank RDIMM is populated in the first slot with white release levers, the third DIMM slot in the channel with
green release levers cannot be populated.
• Up to three LRDIMMs can be populated regardless of rank count.
• Populate DIMM sockets only if a processor is installed. For single-processor systems, sockets A1 to A12 are
available. For dual-processor systems, sockets A1 to A12 and sockets B1 to B12 are available.
• Populate all sockets with white release tabs first, then black, and then green.
• Do not populate the third DIMM socket in a channel with green release tabs, if a quad-rank RDIMM is populated in
the first socket with white release tabs.
• Populate the sockets by highest rank count in the following order — first in sockets with white release levers, then
black, and then green. For example, if you want to mix quad-rank and dual-rank DIMMs, populate quad-rank DIMMs
in the sockets with white release tabs and dual-rank DIMMs in the sockets with black release tabs.
• In a dual-processor configuration, the memory configuration for each processor should be identical. For example, if
you populate socket A1 for processor 1, then populate socket B1 for processor 2, and so on.
• Memory modules of different sizes can be mixed provided that other memory population rules are followed (for
example, 2 GB and 4 GB memory modules can be mixed).
• Populate four DIMMs per processor (one DIMM per channel) at a time to maximize performance.
• If memory modules with different speeds are installed, they will operate at the speed of the slowest installed
memory module(s) or slower depending on system DIMM configuration.
Mode-Specific Guidelines
Four memory channels are allocated to each processor. The allowable configurations depend on the memory mode
selected.
NOTE: x4 and x8 DRAM based DIMMs can be mixed, providing support for RAS features. However, all guidelines
for specific RAS features must be followed. x4 DRAM based DIMMs retain Single Device Data Correction (SDDC)
in memory optimized (independent channel) mode. x8 DRAM based DIMMs require Advanced ECC mode to gain
SDDC.
The following sections provide additional slot population guidelines for each mode.
Advanced ECC (Lockstep)
Advanced ECC mode extends SDDC from x4 DRAM based DIMMs to both x4 and x8 DRAMs. This protects against single
DRAM chip failures during normal operation.
Memory installation guidelines:
• Memory modules must be identical in size, speed, and technology.
• DIMMs installed in memory sockets with white release tabs must be identical and similar rule applies for sockets
with black and green release tabs. This ensures that identical DIMMs are installed in matched pairs - for example,
A1 with A2, A3 with A4, A5 with A6, and so on.
NOTE: Advanced ECC with Mirroring is not supported.
Memory Optimized (Independent Channel) Mode
This mode supports SDDC only for memory modules that use x4 device width and does not impose any specific slot
population requirements.
Memory Sparing
NOTE: To use memory sparing, this feature must be enabled in the System Setup.
In this mode, one rank per channel is reserved as a spare. If persistent correctable errors are detected on a rank, the
data from this rank is copied to the spare rank and the failed rank is disabled.
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