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EM78P458/459
OTP ROM
0 = Calibration disable;
1 = Calibration enable.
• Bit 6 (SIGN2): Polarity bit of offset voltage
0 = Negative voltage;
1 = Positive voltage.
• Bit 5:Bit 3 (VOF2[2]:VOF2[0]): Offset voltage bits
• Bit 1:Bit 0 (PWM2[9]:PWM2[8]): The Most Significant Byte of PWM1 Duty Cycle
A specified value keeps the PWM2 output to stay at high until the value matches with TMR2.
17. IOCB1 ( PRD2: Period of PWM2 )
The content of IOCB1 is a period (time base) of PWM2. The frequency of PWM2 is the reverse of the
period.
18. IOCC1 ( DL1L: the Least Significant Byte ( Bit 7 ~ Bit 0 ) of Duty Cycle Latch of
PWM1 )
The content of IOCC1 is read-only.
19. IOCD1 ( DL1H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle Latch of
PWM1 )
The content of IOCD1 is read-only.
20. IOCE1 ( DL2L: the Least Significant Byte ( Bit 7 ~ Bit 0) of Duty Cycle Latch of
PWM2 )
The content of IOCE1 is read-only.
21. IOCF1 ( DL2H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle Latch of
PWM2 )
The content of IOCF1 is read-only.
This specification is subject to change without prior notice. 07.01.2003 (V1.3)
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