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Contents
x C141-E050-02EN
5.5.2 Phases of operation 5-78
5.5.2.1 Ultra DMA burst initiation phase 5-78
5.5.2.2 Data transfer phase 5-79
5.5.2.3 Ultra DMA burst termination phase 5-79
5.5.3 Ultra DMA data in commands 5-80
5.5.3.1 Initiating an Ultra DMA data in burst 5-80
5.5.3.2 The data in transfer 5-81
5.5.3.3 Pausing an Ultra DMA data in burst 5-81
5.5.3.4 Terminating an Ultra DMA data in burst 5-82
5.5.4 Ultra DMA data out commands 5-85
5.5.4.1 Initiating an Ultra DMA data out burst 5-85
5.5.4.2 The data out transfer 5-85
5.5.4.3 Pausing an Ultra DMA data out burst 5-86
5.5.4.4 Terminating an Ultra DMA data out burst 5-87
5.5.5 Ultra DMA CRC rules 5-89
5.5.6 Series termination required for Ultra DMA 5-91
5.6 Timing 5-92
5.6.1 PIO data transfer 5-92
5.6.2 Single word DMA data transfer 5-94
5.6.3 Multiword DMA data transfer 5-95
5.6.4 Transfer of Ultra DMA data 5-96
5.6.4.1 Starting of Ultra DMA data In Burst 5-96
5.6.4.2 Ultra DMA data burst timing requirements 5-97
5.6.4.3 Sustained Ultra DMA data in burst 5-99
5.6.4.4 Host pausing an Ultra DMA data in burst 5-100
5.6.4.5 Device terminating an Ultra DMA data in burst 5-101
5.6.4.6 Host terminating an Ultra DMA data in burst 5-102
5.6.4.7 Initiating an Ultra DMA data out burst 5-103
5.6.4.8 Sustained Ultra DMA data out burst 5-104
5.6.4.9 Device pausing an Ultra DMA data out burst 5-105
5.6.4.10 Host terminating an Ultra DMA data out burst 5-106
5.6.4.11 Device terminating an Ultra DMA data in burst 5-107
5.6.5 Power-on and reset 5-108