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4 BIOS overview
order in which the POST tests are performed
11 Going to check pressing of <INS> , <END> key during power-on.
12 To init CMOS if "Init CMOS in every boot" is set or <END> key is pressed. Going to disable DMA
and Interrupt controllers.
13 Video display is disabled and port-B is initialized. Chipset init about to begin.
14 8254 timer test about to start.
19 About to start memory refresh test.
1A Memory Refresh line is toggling. Going to check 15us ON/OFF time.
23 To read 8042 input port and disable Megakey GreenPC feature. Make BIOS code segment
writeable.
24 To do any setup before Int vector init.
25 Interrupt vector initialization about to begin. To clear password if necessary.
27 Any initialization before setting video mode to be done.
28 Going for monochrome mode and color mode setting.
2A Different BUSes init (system, static, output devices) to start if present. (Please see Appendix for
details of different BUSes).
2B To give control for any setup required before optional video ROM check.
2C To look for optional video ROM and give control.
2D To give control to do any processing after video ROM returns control.
2E If EGA/VGA not found then do display memory R/W test.
2F EGA/VGA not found. Display memory R/W test about to begin.
30 Display memory R/W test passed. About to look for the retrace checking.
31 Display memory R/W test or retrace checking failed. To do alternate Display memory R/W test.
32 Alternate Display memory R/W test passed. To look for the alternate display retrace checking.
34 Video display checking over. Display mode to be set next.
37 Display mode set. Going to display the power on message.
38 Different BUSes init (input, IPL, general devices) to start if present. (Please see Appendix for details
of different BUSes).
39 Display different BUSes initialization error messages. (Please see Appendix for details of different
BUSes).
3A New cursor position read and saved. To display the Hit <DEL> message.
40 To prepare the descriptor tables.
42 To enter in virtual mode for memory test.