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square-wave output frequency and a
976.562-microsecond periodic interrupt rate.
Status Register B (Hex 00B)
Figure 2-17. Status Register B (Hex 00B)
Bit Function
7 Set
6 Enable periodic interrupt
5 Enable alarm interrupt
4 Enable update-ended interrupt
3 Enable square wave
2 Date mode
1 24-hour mode
0 Enable daylight-saving time
Bit 7 When set to 0, this bit updates the cycle, normally by
advancing the count at a rate of one cycle per second.
When set to 1, it immediately ends any update cycle in
progress, and the program can initialize the 14 time bytes
without any further updates occurring until this bit is set
to 0.
Bit 6 This is a read/write bit that allows an interrupt to occur at
a rate specified by the rate and divider bits in status
register A. When set to 1, this bit enables the interrupt.
The system initializes this bit to 0.
Bit 5 When set to 1, this bit enables the alarm interrupt. The
system initializes this bit to 0.
Bit 4 When set to 1, this bit enables the update-ended
interrupt. The system initializes this bit to 0.
Bit 3 When set to 1, this bit enables the square-wave
frequency as set by the rate-selection bits in status
register A. The system initializes this bit to 0.
Bit 2 This bit indicates whether the binary-coded-decimal (BCD)
or binary format is used for time-and-date calendar
updates. When set to 1, this bit indicates the binary
format. The system initializes this bit to 0.
Bit 1 This bit indicates whether the hours byte is in 12-hour or
24-hour mode. When set to 1, this bit indicates the
24-hour mode. The system initializes this bit to 1.
2-20 ThinkPad 560/560E System Board