Filter
Top Products
© Copyright IBM Corp. 2001 9
Chapter 2. Architecture and technical
overview
The following sections provide more detailed information about the architecture of the Models
6C1 and 6E1. Figure 2-1 shows the high level system block diagram of both models.
Figure 2-1 Model 6C1 and 6E1 - high-level system block diagram
2
Integrated Service
Processor
PCI Bridge
PCI Bridge
External
Ultra3-SCSI
10/100
Ethernet
3rd serial
port
Super
I/O
ISA Bridge
2PCISlots
32 bit
33 MHz
5v
2PCISlots
64-bit
50 MHz
3.3v
I/O Planar
System Planar
Data
Addr/Cntl
MemoryData Bus
Memory
Address
6xx Data Bus
6xx Address Bus
Memory
512 MB - 8 GB
Processor Card
POWER3-II
375 MHz
or
450 MHz
4MBL2
w/ 375 MHz
8MBL2
w/ 450 MHz
Processor Card
POWER3-II
375 MHz
or
450 MHz
4MBL2
w/ 375 MHz
8MBL2
w/ 450 MHz
SCSI Controller
Internal
Ultra3-SCSI
10/100
Ethernet
IDE
CD-
ROM
1PCISlots
64bit
33MHz
5v
16 Bytes @ 93.75 MHz w/ 375 MHz
16 Bytes @ 90 MHz w/ 450MHz
16Bytes @ 93.75MHz w/ 375MHz
16Bytes @ 90 MHz w/ 450 MHz
6xx-MXBus
66 MHz
250 MHz
w/ 375 MHz
225 MHz
w/ 450 MHz
250MHz
w/ 375 MHz
225MHz
w/ 450 MHz