Filter
Top Products
20 Specification Update
Intel
®
80219 General Purpose PCI Processor
Non-Core Errata
Non-Core Errata
1. The ATU Returns Invalid Data for the DWORD that Target Aborted from the
MCU when Using 32-Bit Memory, ECC Enabled and in PCI Mode
The external PCI bus requests a read through the ATU to the MCU, starting at the high DWORD.
Remember the MCU is in 32-bit mode. The ATU requests multiple DWORDs since it pre-fetches, but
starts at the high DWORD address. The MCU issues two DWORDs. First the high, followed by the
low and then a Target Abort, so the DWORD count is two. When the ATU returns the data to the
external PCI agent (in PCI Mode ONLY), the logic ONLY disconnects on 64-byte QWORD
boundaries. Recall the ATU DWORD count is at two. When the external PCI device returns to get
data, the ATU returns the first DWORD and SHOULD disconnect, because it does not have enough
data to get to the next QWORD boundary. It does not do this. Instead, it returns invalid data in the
high DWORD of the second QWORD (data from a previous fetch) and the transaction is corrupted.
This issue occurs when all of the following conditions exist in the MCU:
1. 32-bit memory
2. ECC is enabled
3. The PCI bus is in PCI mode
Workaround: Use 64-bit Memory, PCI-X Mode or ECC disabled.
Status: NoFix.
2. PBI Issue When Using 16-bit PBI Transactions in PCI Mode
Problem: Under certain conditions, in bound burst and non-burst reads and writes from the PCI bus to the
PBI would appear as two writes on the PBI. However, the byte enables are not asserted for the
second write.
This happens when:
1. 80219 is in PCI mode.
2. Another PCI master is attempting to access the PBI behind the 80219.
3. 16-bit mode on PBI.
Workaround: The BE# signals can be used in combination with the PCE#. The BE# prevents the second CE#
from being recognized by the Flash. See the Intel
®
IQ80219 evaluation platform board (IQ80219)
schematic for a circuit design to correct this issue.
Status: NoFix.