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Specification Update 21
Intel
®
80219 General Purpose PCI Processor
Non-Core Errata
3. MCU Pointers are Incorrect following a Restoration from a Power Fail
Problem: This issue occurs when:
1. There is a power failure (not during power management or normal shutdown).
2. When power is restored, the internal MCU pointers to the SDRAM may not be correct.
3. When a read from SDRAM (prior to doing a write to SDRAM) is the first MCU operation
done after the power is restored, the MCU pointers may be incorrect and can be reading the
wrong data.
4. However, when a write to SDRAM is the first MCU operation done after the power is restored,
then the pointers are correct and everything works properly.
Workaround: Following restoration of power after a power failure, ensure that the first MCU operation done is a
write to SDRAM.
Status: NoFix.
4. PMU Does Not Account for when the Arbiter Deasserts GNT# One Cycle
before FRAME#
Problem: One of the countable PMU events is bus acquisition latency for the ATU. There is a condition
where the acquire counter is not stopped even though the ATU starts a transaction. When the arbiter
deasserts GNT# in PCI-X mode, the requestor can still start a transaction for one cycle (due to
allowed pipelining). In this situation, the PMU does not properly detect the FRAME# as the ATU
and continues running the counter.
Workaround: No workaround.
Status: NoFix.
5. Lost Data During Bursts of Large Number of Partials with 32-bit ECC Memory
Problem: When the MCU operates in 32-bit mode only and it is hit by enough partials to cause the input
posted write buffer to fill (in 32-bit mode it holds 512 bytes), the MCU has conditions where it
does NOT disconnect on the IB (internal bus) before overrunning.
When the buffer overruns, the MCU momentarily thinks it is empty, allowing the refresh to occur,
but also causing all data to be lost for the rest of the burst. The ATU continues to throw data at the
MCU, but this data is lost.
This is strictly a 32-bit memory ECC on mode issue, as this is the only way to fill the entire buffer
since all buffers on the IB are 1 K in size (except the MCU when operating in 32-bit DDR mode).
The DMA, AAU, and core cannot cause the situation in 32-bit mode because they only issue up to
two partials in their burst before disconnecting. In these situations, the MCU will drain enough data
to prevent buffer overrun.
Workaround: Use 64-bit memory or ECC disabled.
Status: NoFix.