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Specification Update 27
HSD35. PLATFORM_POWER_LIMIT MSR Not Visible
Problem: The PLATFORM_POWER_LIMIT MSR (615H) is used to control the PL3 (power limit 3)
mechanism of the processor. Due to this erratum, this MSR is not visible to software.
Implication: Software is unable to read or write the PLATFORM_POWER_LIMIT MSR. If software
attempts to access this MSR, a general protection fault will occur.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD36. LPDDR Memory May Report Incorrect Temperature
Problem: When any of the four possible LPDDR ranks are not populated, the unpopulated ranks
will report a default temperature of 85C as a three bit value of 011b. If the system has
unpopulated ranks the temperature of memory will be reported as 85C
in PCU_CR_DDR_DIMM_HOTTEST_ABSOLUTE (MCHBAR Bus 0; Device 0; Function 0;
offset 58B8H) in bits [5:7], until any of the populated ranks report a higher
temperature than this.
Implication: When the memory temperature is less than or equal to 85C it may be reported as
85C. This erratum does not affect DDR3 and DDR3L memory types.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD37. PCIe* Host Bridge DID May Be Incorrect
Problem: The PCIe Host Bridge DID register (Bus 0; Device 0; Offset 2H) contents may be
incorrect after a Package C7 exit.
Implication: Software that depends on the Host Bridge DID value may not behave as expected after
a Package C7 exit.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD38. TSC May be Incorrect After a Deep C-State Exit
Problem: On exiting from Package C6 or deeper, the processor may incorrectly restore the TSC
(Time Stamp Counter).
Implication: Software using the TSC may produce incorrect result and/or may not behave as
expected.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD39. PCIe* Controller May Initiate Speed Change While in DL_Init State
Causing Certain PCIe Devices to Fail to Train
Problem: The PCIe controller supports hardware autonomous speed change capabilities. Due to
this erratum, the PCIe controller may initiate speed change while in the DL_Init state
which may prevent link training for certain PCIe devices.
Implication: Certain PCIe devices may fail to complete DL_Init causing the PCIe link to fail to train.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.