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Specification Update 39
HSD87. Intel
®
TSX Instructions May Cause Unpredictable System behavior
Problem: Under certain system conditions, Intel TSX (Transactional Synchronization Extensions)
instructions may result in unpredictable system behavior.
Implication: Due to this erratum, use of Intel TSX may result in unpredictable behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD88. Event Injection by VM Entry May Use an Incorrect B Flag for SS
Problem: The stack accesses made by VM-entry event injection may use an incorrect value for
the B flag (default stack-pointer size and upper bound) for the stack segment (SS).
Implication: An affected stack access may use an incorrect address or an incorrect segment upper
bound. This may result in unpredictable system behavior.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Table of Changes.
HSD89. A Fault in SMM May Result in Unpredictable System Behavior
Problem: The value of the SS register as well as the current privilege level (CPL) may be
incorrect following a fault in SMM (system-management mode). The erratum can occur
only if a fault occurs following an SMI (system-management interrupt) and before
software has loaded the SS register (e.g., with the MOV SS instruction).
Implication: This erratum may cause unpredictable system behavior. Intel has not observed this
erratum with any commercially available software.
Workaround: None identified
Status: For the steppings affected, see the Summary Table of Changes.
HSD90. Processor Frequency is Unexpectedly Limited Below Nominal P1 When
cTDP Down is Enabled
Problem: When cTDP (Configurable Thermal Design Power) Down is enabled on a processor
branded as Core
®
i3 or Pentium
®
, the processor frequency will be limited to cTDP
Down P1 frequency (Max Non-Turbo Frequency) when it should be able to operate
between the cTDP Down frequency P1 and the nominal P1 frequency.
Implication: When cTDP is enabled, the processor cannot achieve expected frequencies.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
HSD91. PMI May be Signaled More Than Once For Performance Monitor
Counter Overflow
Problem: Due to this erratum, PMI (Performance Monitoring Interrupt) may be repeatedly issued
until the counter overflow bit is cleared in the overflowing counter.
Implication: Multiple PMIs may be received when a performance monitor counter overflows.
Workaround: None identified. If the PMI is programmed to generate an NMI, software may delay the
EOI (end-of- Interrupt) register write for the interrupt until after the overflow
indications have been cleared.
Status: For the steppings affected, see the Summary Table of Changes.